82801DB Datasheet, PDF (401/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

USB UHCI Controllers Registers
11.1.4
11.1.5
11.1.6
STA—Device Status Register (USB—D29:F0/F1/F2)
Address Offset:
Default Value:
06–07h
0280h
Attribute:
Size:
R/WC, RO
16 bits
Bit
Description
15:14
13
Reserved as 00b. Read Only.
Received Master Abort (RMA) — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = USB, as a master, generated a master-abort.
12 Reserved. Always read as 0.
Signaled Target Abort (STA) — R/WC.
11 0 = Software clears this bit by writing a 1 to the bit location.
1 = USB function is targeted with a transaction that the ICH4 terminates with a target abort.
DEVSEL# Timing Status (DEV_STS) — RO: This 2-bit field defines the timing for DEVSEL#
10:9 assertion. These read only bits indicate the ICH4's DEVSEL# timing when performing a positive
decode. ICH4 generates DEVSEL# with medium timing for USB.
8 Data Parity Error Detected (DPED) — RO. Reserved as 0.
7 Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
6 User Definable Features (UDF) — RO. Reserved as 0.
5 66 MHz Capable (66MHZ_CAP) — RO. Reserved as 0.
4:0 Reserved
RID—Revision Identification Register (USB—D29:F0/F1/F2)
Address Offset:
Default Value:
08h
See Bit Description
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Revision Identification Value — RO. Refer to the ICH4 specification update for the value of the
Revision ID Register.
PI—Programming Interface (USB—D29:F0/F1/F2)
Address Offset:
09h
Default Value:
00h
Attribute:
Size:
RO
8 bits
Bit
Description
Programming Interface — RO.
7:0
00h = No specific register level programming interface defined.
Intel^® 82801DB ICH4 Datasheet
401