82801DB Datasheet, PDF (424/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

EHCI Controller Registers (D29:F7)
12.1.17
NXT_PTR1—Next Item Pointer #1 Register
(USB EHCI—D29:F7)
Address Offset: 51h
Default Value: 58h
Attribute: R/W-Special
Size:
8 bits
Bit
Description
Next Item Pointer #1 Value — R/W-Special. This register defaults to 58h, which indicates that the
next capability registers begin at configuration offset 58h. This register is writable when the
7:0
WRT_RDONLY bit is set. This allows BIOS to effectively hide the Debug Port capability registers, if
necessary. This register should only be written during system initialization before the plug-and-play
software has enabled any master-initiated traffic. Only values of 58h (Debug Port visible) and 00h
(Debug Port invisible) are expected to be programmed in this register.
12.1.18
PWR_CAP—Power Management Capabilities Register
(USB EHCI—D29:F7)
Address Offset: 52–53h
Default Value: C9C2h
Attribute: R/W-Special
Size:
16 bits
Bit
Description
15:11
10
9
8:6
5
4
3
2:0
PME Support — R/W-Special. This 5-bit field indicates the power states in which the function may
assert PME#. The ICH4 EHC does not support the D1 or D2 states. For all other states, the ICH4
EHC is capable of generating PME#. Software should never need to modify this field.
D2 Support — R/W-Special.
0 = D2 State is not supported
1 = D2 State is supported
D1 Support — R/W-Special.
0 = D1 State is not supported
1 = D1 State is supported
Auxiliary Current — R/W-Special. The ICH4 EHC reports 375 mA maximum Suspend well current
required when in the D3cold state. This value can be written by BIOS when a more accurate value is
known.
DSI — R/W-Special. The ICH4 reports 0, indicating that no device-specific initialization is required.
Reserved
PME Clock — R/W-Special. The ICH4 reports 0, indicating that no PCI clock is required to generate
PME#.
Version — R/W-Special. The ICH4 reports 010b, indicating that it complies with Revision 1.1 of the
PCI Power Management Specification.
NOTES:
1. Normally, this register is read-only to report capabilities to the power management software. To report
different power management capabilities, depending on the system in which the ICH4ICH4 is used, bits 15:11
and 8:6 in this register are writable when the WRT_RDONLY bit is set. The value written to this register does
not affect the hardware other than changing the value returned during a read.
2. Reset: core well, but not D3-to-D0 warm reset.
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Intel^® 82801DB ICH4 Datasheet