82801DB Datasheet, PDF (461/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

SMBus Controller Registers (D31:F3)
13.2.9
RCV_SLVA—Receive Slave Address Register
Register Offset: 09h
Default Value: 44h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8 bits
Resume
Bit
Description
7 Reserved
SLAVE_ADDR — R/W. This field is the slave address that the ICH4 decodes for read and write
6:0 cycles. the default is not 0, so the SMBus Slave Interface can respond even before the processor
comes up (or if the processor is dead). This register is cleared by RSMRST#, but not by PCIRST#.
13.2.10
.
SLV_DATA—Receive Slave Data Register
Register Offset:
Default Value:
Lockable:
0Ah
0000h
No
Attribute:
Size:
Power Well:
RO
16 bits
Resume
This register contains the 16-bit data value written by the external SMBus master. The processor
can then read the value from this register. This register is reset by RSMRST#, but not PCIRST#.
Bit
Description
15:8 Data Message Byte 1 (DATA_MSG1) — RO. See Section 5.18.7 for a discussion of this field.
7:0 Data Message Byte 0 (DATA_MSG0) — RO. See Section 5.18.7 for a discussion of this field.
13.2.11
.
AUX_STS—Auxiliary Status Register
Register Offset: 0Ch
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
RW/C
8 bits
Resume
Bit
Description
7:1 Reserved
CRC Error (CRCE) — R/WC.
0 = Software clears this bit by writing a 1 to it.
0 ^{1 = This bit is set if a received message contained a CRC error. When this bit is set, the DERR bit of}
the host status register will also be set. This bit will be set by the controller if a software abort
occurs in the middle of the CRC portion of the cycle or an abort happens after the ICH4 has
received the final data bit transmitted by an external slave.
Intel^® 82801DB ICH4 Datasheet
461