82801DB Datasheet, PDF (229/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
Note: Throughout this document, references to D31:F5 indicate that the audio function exists in PCI
Device 31, Function 5. References to D31:F6 indicate that the modem function exists in PCI
Device 31, Function 6.
Note:
Throughout this document, references to tertiary, third, or triple codecs refer to the third codec in
the system connected to the AC_SDIN[2] pin. The AC ’97 2.3 specification refers to non-primary
codecs as multiple secondary codecs. To avoid confusion and excess verbiage this datasheet refers
to it as the third or tertiary codec.
Figure 5-20. Intel^® ICH4 Based Audio Codec ’97 Specification, Revision 2.3
Audio In (Record)
PC
Audio Out (6 Channel Playback)
S/PDIF* Output
Modem
Mic.2
Mic.1
5.19.1
PCI Power Management
This Power Management section applies for all AC ’97 controller functions. After a power
management event is detected, the AC ’97 controller will wake the host system. The sections
below describe these events and the AC ’97 controller power states.
Device Power States
The AC ’97 controller supports D0 and D3 PCI Power Management states. Notes regarding the
Intel ICH4 AC ’97 controller implementation of the Device States:
1. The AC ’97 controller hardware does not inherently consume any more power when it is in the
D0 state than it does in D3 state. However, software can halt the DMA engine prior to entering
these low power states such that the maximum power consumption is reduced.
2. In the D0 state, all implemented AC ’97 controller features are enabled.
3. In D3 state, accesses to the AC ’97 controller memory-mapped or I/O range result in master
abort.
4. In D3 state, the AC ’97 controller interrupt must never assert for any reason. The internal
PME# signal is used to signal wake events, etc.
5. When the Device Power State field is written from D3_HOT to D0, an internal reset is generated.
See Section 14.1 for general rules on the effects of this reset.
6. AC ’97 STS bit will be set only when the audio or modem resume events were detected and
their respective PME enable bits were set.
7. GPIO Status change interrupt no longer has a direct path to AC ’97 STS bit. This will cause a
wake up event only if the modem controller was in D3
8. Resume events on AC_SDIN[2:0] will cause resume interrupt status bits to be set only if their
respective controllers are not in D3.
9. Edge detect logic will prevent the interrupts from being asserted in case AC ’97 controller is
switched from D3 to D0 after a wake event.
10. Once the interrupt status bits are set, they will cause PIRQB# if their respective enable bits
were set. One of the audio or the modem drivers will handle the interrupt.
Intel^® 82801DB ICH4 Datasheet
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