82801DB Datasheet, PDF (159/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.14 General Purpose I/O
5.14.1 GPIO Mapping
Table 5-51. GPIO Implementation (Sheet 1 of 2)
GPIO
Type
GPI[0]
Input
Only
GPI[1]
Input
Only
GPI[2:5]
Input
Only
GPI[6]
Input
Only
GPI[7]
Input
Only
GPI[8]
Input
Only
GPIO[9:10] N/A
GPI[11]
Input
Only
GPI[12]
Input
Only
GPI[13]
Input
Only
GPIO[14:15] N/A
Alternate
Function ⁽¹⁾
REQ[A]#
REQ[B]# or
REQ[5]#
PIRQ[E:H]#
Unmuxed
Unmuxed
N/A
SMBALERT#
Unmuxed
Unmuxed
N/A
Power
Well
Tolerant
Core
5.0 V
Core
5.0 V
Core
5.0 V
Core
5.0 V
Core
5.0 V
Resume 3.3 V
N/A
Resume 3.3 V
Resume 3.3 V
Resume 3.3 V
N/A
Notes
• GPIO_USE_SEL bit 0 enables REQ/
GNT[A]# pair.
• Input active status read from
GPE0_STS register bit 0.
• Input active high/low set through
GPI_INV register bit 0.
• GPIO_USE_SEL bit 1 enables REQ/
GNT[B]# pair ⁽³⁾.
• Input active status read from
GPE0_STS register bit 1.
• Input active high/low set through
GPI_INV register bit 1.
• GPIO_USE_SEL bits [2:5] enable
PIRQ[E:H]#.
• Input active status read from
GPE0_STS register bits [2:5].
• Input active high/low set through
GPI_INV register bits [2:5].
• Input active status read from
GPE0_STS register bit 6.
• Input active high/low set through
GPI_INV register bit 6.
• Input active status read from
GPE0_STS register bit 7.
• Input active high/low set through
GPI_INV register bit 7
• Input active status read from
GPE0_STS register bit 8.
• Input active high/low set through
GPI_INV register bit 8.
• Not implemented
• GPIO_USE_SEL bit 11 enables
SMBALERT#
• Input active status read from
GPE0_STS register bit 11.
• Input active high/low set through
GPI_INV register bit 11.
• Input active status read from
GPE0_STS register bit 12.
• Input active high/low set through
GPI_INV register bit 12.
• Input active status read from
GPE0_STS register bit 13.
• Input active high/low set through
GPI_INV register bit 13.
• Not Implemented
Intel^® 82801DB ICH4 Datasheet
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