82801DB Datasheet, PDF (228/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
.
Table 5-99. Features Supported by Intel^® ICH4
Feature
Description
System Interface
Power
Management
• Isochronous low latency bus master memory interface
• Scatter/gather support for word-aligned buffers in memory.
(all mono or stereo 20-bit and 16-bit data types are supported, no 8-bit data types are
supported).
• Data buffer size in system memory from 3 to 65535 samples per input.
• Data buffer size in system memory from 0 to 65535 samples per output.
• Independent PCI audio and modem functions with configuration and IO spaces.
• AC ’97 codec registers are shadowed in system memory via driver.
• AC ’97 codec register accesses are serialized via semaphore bit in PCI IO space
(new accesses are not allowed while a prior access is still in progress).
• Power management via PCI Power Management
PCI Audio
Function
PCI Modem
function
• Read/write access to audio codec registers 00h–3Ah and vendor registers 5Ah–7Eh.
• 20-bit stereo PCM output, up to 48 kHz (L,R, Center, Sub-woofer, L-rear and R-rear
channels on slots 3,4,6,7,8,9,10,11).
• 16-bit stereo PCM input, up to 48 kHz (L,R channels on slots 3,4).
• 16-bit mono mic in w/ or w/o mono mix, up to 48 kHz (L,R channel, slots 3,4) (mono
mix supports mono hardware AEC reference for speakerphone).
• 16-bit mono PCM input, up to 48 kHz from dedicated mic ADC (slot 6)
(supports speech recognition or stereo hardware AEC ref for speakerphone).
• During cold reset, AC_RST# is held low until after POST and software deassertion of
AC_RST# (supports passive PC_BEEP to speaker connection during POST).
• Read/write access to modem codec registers 3Ch–58h and vendor registers 5Ah–
7Eh.
• 16-bit mono modem line1 output and input, up to 48 kHz (slot 5).
• Low latency GPIO[15:0] via hardwired update between slot 12 and PCI IO register.
• Programmable PCI interrupt on modem GPIO input changes via slot 12 GPIO_INT.
• SCI event generation on AC_SDIN[2:0] wake-up signals.
AC-link
• Supports AC ’97 2.3 AC-link interface.
• Variable sample rate output support via AC ’97 SLOTREQ protocol
(slots 3,4,5,6,7,8,9,10,11).
• Variable sample rate input support via monitoring of slot valid tag bits (slots 3,4,5,6)
• 3.3 V digital operation meets AC ’97 2.3 DC switching levels.
• AC-link IO driver capability meets AC ’97 2.3 triple codec specifications.
• Codec register status reads must be returned with data in the next AC-link frame, per
the AC ’97 2.3 specification.
Multiple Codec
• Triple codec addressing: All AC ’97 Audio codec register accesses are addressable to
codec ID 00 (primary), codec ID 01 (secondary), or codec ID 10 (tertiary).
• Modem codec addressing: All AC ’97 Modem codec register accesses are
addressable to codec ID 00 (primary) or codec ID 01 (secondary).
• Triple codec receive capability via AC_SDIN[2:0] pins
(AC_SDIN[2:0] frames are internally validated, synch’d, and OR’d depending on the
Steer Enable bit status in the SDM register).
• AC_SDIN mapping to DMA engine mapping capability allows for simultaneous input
from three different audio codecs.
NOTES:
1. Audio Codec IDs are remappable and not limited to 00,01,10.
2. Modem Codec IDs are remappable and limited to 00,01.
3. When using multiple codecs, the Modem Codec must be ID 01.
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Intel^® 82801DB ICH4 Datasheet