82801DB Datasheet, PDF (441/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

EHCI Controller Registers (D29:F7)
12.2.2.4
FRINDEX—Frame Index Register
Offset:
Default Value:
CAPLENGTH + 0C–0Fh
00000000h
Attribute: R/W
Size:
32 bits
The SOF frame number value for the bus SOF token is derived or alternatively managed from this
register. Refer to Section 4 of the EHCI specification for a detailed explanation of the SOF value
management requirements on the host controller. The value of FRINDEX must be within 125 µs
(1 micro-frame) ahead of the SOF token value. The SOF value may be implemented as an 11-bit
shadow register. For this discussion, this shadow register is 11 bits and is named SOFV. SOFV
updates every 8 micro-frames. (1 millisecond). An example implementation to achieve this
behavior is to increment SOFV each time the FRINDEX[2:0] increments from 0 to 1.
Software must use the value of FRINDEX to derive the current micro-frame number, both for high-
speed isochronous scheduling purposes and to provide the get micro-frame number function
required to client drivers. Therefore, the value of FRINDEX and the value of SOFV must be kept
consistent if chip is reset or software writes to FRINDEX. Writes to FRINDEX must also write-
through FRINDEX[13:3] to SOFV[10:0]. In order to keep the update as simple as possible,
software should never write a FRINDEX value where the three least significant bits are 111b or
000b.
Note:
This register is used by the host controller to index into the periodic frame list. The register updates
every 125 microseconds (once each micro-frame). Bits [12:3] are used to select a particular entry in
the Periodic Frame List during periodic schedule execution. The number of bits used for the index
is fixed at 10 for the ICH4 since it only supports 1024-entry frame lists. This register must be
written as a DWord. Word and byte writes produce undefined results. This register cannot be
written unless the Host controller is in the Halted state as indicated by the HCHalted bit (USB
EHCI STS register). A write to this register while the Run/Stop bit is set to a 1 (USB EHCI CMD
register) produces undefined results. Writes to this register also effect the SOF value. For details,
see Chapter 4 of the Enhanced Host Controller Interface (EHCI) Specification for Universal Serial
Bus.
Bit
Description
31:14
13:0
Reserved
Frame List Current Index/Frame Number — R/W. The value in this register increments at the end
of each time frame (e.g., micro-frame). Bits [12:3] are used for the Frame List current index. This
means that each location of the frame list is accessed 8 times (frames or micro-frames) before
moving to the next index.
Intel^® 82801DB ICH4 Datasheet
441