82801DB Datasheet, PDF (147/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
Sleep Button
The ACPI specification defines an optional Sleep button. It differs from the power button in that it
only is a request to go from S0 to S1–S4 (not S5). Also, in an S5 state, the Power Button can wake
the system, but the Sleep Button cannot.
Although the ICH4 does not include a specific signal designated as a Sleep Button, one of the
GPIO signals can be used to create a “Control Method” Sleep Button. See the ACPI specification
for implementation details.
5.12.8.2 Ring Indicate (RI#)
The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states. Table 5-45 shows
when the wake event is generated or ignored in different states. If in the G0/S0/Cx states, the ICH4
will generate an interrupt based on RI# active and the interrupt will be set up as a Break event.
Table 5-45. Transitions Due to RI# Signal
Present State
S0
S1–S5
Event
RI# Active
RI# Active
RI_EN
X
0
1
Event
Ignored
Ignored
Wake Event
Note: Filtering/Debounce on RI# will not be done in the ICH4. It can be in modem or external.
5.12.8.3
PCI Power Management Event (PME#)
The PME# signal comes from a PCI device to request that the system be restarted. The PME#
signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs when the PME#
signal goes from high-to-low. No event is caused when it goes from low-to-high.
In the EHCI controller, there is an internal PME_B0 bit. This is separate from the external PME#
signal and can cause the same effect.
5.12.8.4
SYS_RESET# Signal
SYS_RESET# is a new pin on the ICH4 that is used to eliminate extra glue logic on the board.
Before the addition of this pin, a system reset was activated by external glue forcing the PWROK
signal low after the reset button was pressed. This pin eliminates the need for that glue. As such, a
SYS_RESET# event should look internally to our chip and externally to the system as if PWROK
had gone low.
When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the ICH4
attempts to perform a “graceful” reset, by waiting up to 25 ms for the SMBus to go idle. If the
SMBus is idle when the pin is detected active, the reset occurs immediately, otherwise the counter
starts. If at any point during the count the SMBus goes idle, the reset occurs. If, however, the
counter expires and the SMBus is still active, a reset is forced upon the system even though activity
is still occurring.
Once a reset of this type has occurred, it cannot occur again until SYS_RESET# has been detected
inactive after the debounce logic, and the system is back to a full S0 state as indicated by all of the
PWROK inputs being active.
Intel^® 82801DB ICH4 Datasheet
147