82801DB Datasheet, PDF (65/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Intel^® ICH4 and System Clock Domains
Intel^® ICH4 and System Clock Domains4
Table 4-1 shows the system clock domains. Figure 4-1 shows the assumed connection of the
various system components, including the clock generator in both desktop and mobile systems. For
complete details of the system clocking solution refer to the system’s clock generator component
specification.
Table 4-1. Intel^® ICH4 and System Clock Domains
Clock
Domain
Frequency
Source
Usage
ICH4
CLK66
ICH4
PCICLK
66 MHz
33 MHz
System PCI
33 MHz
ICH4
CLK48
48 MHz
ICH4
CLK14
14.31818 MHz
ICH4
AC_BIT_CLK
12.288 MHz
ICH4
APICCLK
33 MHz
LAN_CLK 5 to 50 MHz
Main Clock
Generator
Main Clock
Generator
Main Clock
Generator
Main Clock
Generator
Main Clock
Generator
AC ’97 Codec
Main Clock
Generator
LAN Connect
Component
Hub I/F, processor I/F. AGP. Shut off during S3 or below.
Free-running PCI Clock to ICH4. This clock remains on
during S0 and S1 state, and is expected to be shut off
during S3 or below .
PCI Bus, LPC I/F. These only go to external PCI and LPC
devices.
Super I/O, USB controllers. Expected to be shut off during
S3 or below
Used for ACPI timer. Expected to be shut off during S3 or
below
AC-link. Generated by AC ’97 Codec. Can be shut by
codec in D3. Expected to be shut off during S3 or below
Used for ICH4-CPU interrupt messages. Runs up to
33 MHz. Expected to be shut off during S3 or below
Generated by the LAN Connect component. Expected to
be shut off during S3 or below
Intel^® 82801DB ICH4 Datasheet
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