82801DB Datasheet, PDF (199/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
Note: The ADE does not fetch data when a QH is encountered in the Ping state. An Ack handshake in
response to the Ping results in the ADE writing the QH to the Out state, which results in the
fetching and delivery of the Out Data on the next iteration through the asynchronous list.
Note: Once the ADE checks the length of an asynchronous packet against the remaining time in the
microframe (late-start check) and decides that there is not enough time to run it on the wire, then
the EHC stops all activity on the USB ports for the remainder of that microframe.
Note:
Once the ADE detects an “empty” asynchronous schedule as described in Chapter 4 of the
Enhanced Host Controller Interface (EHCI) Specification for Universal Serial Bus, it implements
a waking mechanism like the one in the example. The amount of time that the ADE “sleeps” is
10 µs ± 30 ns.
5.17.3.2.2 Write Policies for Asynchronous DMA
The Asynchronous DMA engine performs writes for the following reasons.
Memory Structure
Size
(DWords)
Comments
Asynchronous
Queue Head Overlay
Asynchronous
Queue Head Status
Write
Asynchronous qTD
Status Write
In Data
14
34
3
Up to 1297
Only the 64-bit addressing format is supported. DWords 0C:43h are
written.
DWords 14:1Fh are written.
DWords 04:0Fh are written. PID Code, IOC, Buffer Pointer (Page 0),
and Alt. Next qTD Pointers are re-written with the original value.
The Intel^® ICH4 breaks data writes down into 16 DWord aligned
chunks.
NOTES:
1. The Asynchronous DMA Engine (ADE) will only generate writes after a transaction is executed on USB.
2. Status writes are always performed after In Data writes for the same transaction.
5.17.4
Data Encoding and Bit Stuffing
See Chapter 8 of the Universal Serial Bus (USB) Specification, Revision 2.0.
5.17.5
Packet Formats
See Chapter 8 of the Universal Serial Bus (USB) Specification, Revision 2.0.
Intel^® 82801DB ICH4 Datasheet
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