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82801DB Datasheet, PDF (573/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4) | |||
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Register Index
Table A-3. Intel® ICH4 Variable I/O Registers (Sheet 1 of 6)
Register Name
Offset
Datasheet Location
LAN Control/Status Registers (CSR) may be mapped to either I/O space or memory space.
LAN CSR at CSR_IO_BASE + Offset or CSR_MEM_BASE + Offset. CSR_MEM_BASE set in Section 7.1.11,
âCSR_MEM_BASE CSR â Memory-Mapped Base Address Register (LAN ControllerâB1:D8:F0)â on page 7-256
CSR_IO_BASE set in Section 7.1.12, âCSR_IO_BASE â CSR I/O-Mapped Base Address Register (LAN Controllerâ
B1:D8:F0)â on page 7-257
SCB Status Word
SCB Command Word
SCB General Pointer
PORT
EEPROM Control Register
MDI Control Register
Receive DMA Byte Count
Early Receive Interrupt
Flow Control Register
PMDR
General Control
General Status
01hâ00h
03hâ02h
07hâ04h
OBhâ08h
0Fhâ0Eh
13hâ10h
17hâ14h
18h
1Ahâ19h
1Bh
1Ch
1Dh
Section 7.2.1, âSystem Control Block Status Word Registerâ on page 7-262
Section 7.2.2, âSystem Control Block Command Word Registerâ on
page 7-264
Section 7.2.3, âSystem Control Block General Pointer Registerâ on
page 7-266
Section 7.2.4, âPORT Registerâ on page 7-266
Section 7.2.5, âEEPROM Control Registerâ on page 7-267
Section 7.2.6, âManagement Data Interface (MDI) Control Registerâ on
page 7-268
Section 7.2.7, âReceive DMA Byte Count Registerâ on page 7-269
Section 7.2.8, âEarly Receive Interrupt Registerâ on page 7-269
Section 7.2.9, âFlow Control Registerâ on page 7-270
Section 7.2.10, âPower Management Driver (PMDR) Registerâ on
page 7-271
Section 7.2.11, âGeneral Control Registerâ on page 7-272
Section 7.2.12, âGeneral Status Registerâ on page 7-272
Power Management I/O Registers at PMBASE+Offset
PMBASE set in Section 9.1.10, âPMBASEâACPI Base Address (LPC I/FâD31:F0)â on page 9-296
PM1 Status
PM1 Enable
PM1 Control
PM1 Timer
Processor Control
Level 2 Register
General Purpose Event 0 Status
General Purpose Event 0
Enables
SMI# Control and Enable
SMI Status Register
Alternate GPI SMI Enable
Alternate GPI SMI Status
00â01h
02â03h
04â07h
08â0Bh
10hâ13h
14h
28â2Bh
2Câ2Fh
30â31h
34â35h
38â39h
3Aâ3Bh
Section 9.8.3.1, âPM1_STSâPower Management 1 Status Registerâ on
page 9-354
Section 9.8.3.2, âPM1_ENâPower Management 1 Enable Registerâ on
page 9-356
Section 9.8.3.3, âPM1_CNTâPower Management 1 Control Registerâ on
page 9-357
Section 9.8.3.4, âPM1_TMRâPower Management 1 Timer Registerâ on
page 9-358
Section 9.8.3.5, âPROC_CNTâProcessor Control Registerâ on page 9-358
Section 9.8.3.6, âLV2 â Level 2 Registerâ on page 9-359
Section 9.8.3.7, âGPE0_STSâGeneral Purpose Event 0 Status Registerâ on
page 9-360
Section 9.8.3.8, âGPE0_ENâGeneral Purpose Event 0 Enables Registerâ on
page 9-362
Section 9.8.3.9, âSMI_ENâSMI Control and Enable Registerâ on page 9-363
Section 9.8.3.10, âSMI_STSâSMI Status Registerâ on page 9-365
Section 9.8.3.11, âALT_GP_SMI_ENâAlternate GPI SMI Enable Registerâ
on page 9-367
Section 9.8.3.12, âALT_GP_SMI_STSâAlternate GPI SMI Status Registerâ
on page 9-367
Intel® 82801DB ICH4 Datasheet
573
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