82801DB Datasheet, PDF (477/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

AC ’97 Audio Controller Registers (D31:F5)
14.1.20 CFG—Configuration Register (Audio—D31:F5)
Address Offset: 41h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8 bits
Core
This register is used to specify the ID for the secondary and tertiary codecs for I/O accesses. This
register is not affected by the D3_HOT to D0 transition.
Bit
Description
7:1 Reserved — RO.
I/O Space Enable (IOSE) — R/W.
0
0 = Disable. The IOS bit at offset 04h and the I/O space BARs at offset 10h and 14h become read
only registers. (Default)
1 = Enable. BIOS must explicitly set this bit to allow a legacy driver to work.
14.1.21
PID—PCI Power Management Capability ID Register
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
50h
0001h
No
Attribute:
Size:
Power Well:
RO
16 bits
Core
Bit
Description
15:8 Next Capability (NEXT) — RO. This field indicates that the next item in the list is at offset 00h.
7:0
Capability ID (CAP) — RO. This field indicates that this pointer is a message signaled interrupt
capability.
14.1.22
PC—Power Management Capabilities Register
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
52h
C9C2h
No
Attribute:
Size:
Power Well:
This register is not affected by the D3_HOT to D0 transition.
RO
16 bits
Core
Bit
Description
15:11 PME Support — RO. This field indicates PME# can be generated from all D states.
10:9 Reserved.
8:6
Auxiliary Current — RO. This field reports 375 mA maximum Suspend well current required when in
the D3cold state.
5
Device Specific Initialization (DSI) — RO. This bit indicates that no device-specific initialization is
required.
4 Reserved — RO.
3 PME Clock — RO. This bit indicates that PCI clock is not required to generate PME#.
2:0 Version — RO. Indicates support for Revision 1.1 of the PCI Power Management Specification.
Intel^® 82801DB ICH4 Datasheet
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