82801DB Datasheet, PDF (462/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

SMBus Controller Registers (D31:F3)
13.2.12
.
AUX_CTL—Auxiliary Control Register
Register Offset: 0Dh
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8 bits
Resume
Bit
Description
7:2 Reserved
Enable 32-byte Buffer (E32B)— R/W.
0 = Disable.
1 _{1 = Enable. The Host Block Data register is a pointer into a 32-byte buffer, as opposed to a single}
register. This enables the block commands to transfer or receive up to 32-bytes before the ICH4
generates an interrupt.
Automatically Append CRC (AAC) — R/W.
0 ^{0 = Disable.}
1 = Enable. The ICH4 automatically appends the CRC. This bit must not be changed during SMBus
transactions, or undetermined behavior will result
13.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register
Register Offset: 0Eh
Default Value: See below
Attribute:
Size:
R/W, RO
8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit
Description
7:3 Reserved
SMLINK_CLK_CTL — R/W.
0 = ICH4 drives the SMLINK[0] pin low, independent of what the other SMLINK logic would otherwise
2
indicate for the SMLINK[0] pin.
1 = The SMLINK[0] pin is not overdriven low. The other SMLINK logic controls the state of the pin.
(Default)
SMLINK1_CUR_STS — R/W. This pin returns the value on the SMLINK[1] pin. This allows software
to read the current state of the pin. Default value is dependent on an external signal level.
1 _{0 = Low}
1 = High
SMLINK0_CUR_STS — RO. This pin returns the value on the SMLINK[0] pin. This allows software to
read the current state of the pin. Default value is dependent on an external signal level.
0 _{0 = Low}
1 = High
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Intel^® 82801DB ICH4 Datasheet