82801DB Datasheet, PDF (22/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

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SOF Packet ................................................................................................. 188
Data Packet Format..................................................................................... 188
Bits Maintained in Low Power States .......................................................... 192
USB Legacy Keyboard State Transitions .................................................... 194
UHCI vs. EHCI............................................................................................. 195
Debug Port Behavior ................................................................................... 206
Quick Protocol ............................................................................................. 211
Send / Receive Byte Protocol without PEC ................................................. 211
Send/Receive Byte Protocol with PEC ........................................................ 212
Write Byte/Word Protocol without PEC........................................................ 212
Write Byte/Word Protocol with PEC............................................................. 213
Read Byte/Word Protocol without PEC ....................................................... 214
Read Byte/Word Protocol with PEC ............................................................ 214
Process Call Protocol without PEC.............................................................. 215
Process Call Protocol with PEC................................................................... 216
Block Read/Write Protocol without PEC ...................................................... 217
Block Read/Write Protocol with PEC ........................................................... 218
I²C Block Read ............................................................................................ 219
Enable for SMBALERT# .............................................................................. 221
Enables for SMBus Slave Write and SMBus Host Events........................... 221
Enables for the Host Notify Command ........................................................ 221
Slave Write Cycle Format ............................................................................ 223
Slave Write Registers .................................................................................. 223
Command Types ......................................................................................... 224
Read Cycle Format...................................................................................... 225
Data Values for Slave Read Registers ........................................................ 225
Host Notify Format....................................................................................... 227
Features Supported by Intel^® ICH4 ............................................................. 228
AC ’97 Signals ............................................................................................. 231
Input Slot 1 Bit Definitions............................................................................ 235
Output Tag Slot 0......................................................................................... 237
AC-link State during PCIRST#..................................................................... 240
PCI Devices and Functions ......................................................................... 244
Fixed I/O Ranges Decoded by Intel^® ICH4.................................................. 246
Variable I/O Decode Ranges ....................................................................... 248
Memory Decode Ranges from Processor Perspective ................................ 249
LAN Controller PCI Configuration Register Address Map
(LAN Controller—B1:D8:F0) ........................................................................ 251
Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM... 257
Data Register Structure ............................................................................... 261
Intel^® ICH4 Integrated LAN Controller CSR Space ..................................... 262
Self-Test Results Format ............................................................................. 267
Statistical Counters...................................................................................... 273
Hub Interface PCI Configuration Register Address Map
(HUB-PCI—D30:F0) .................................................................................... 275
LPC I/F PCI Configuration Register Address Map (LPC I/F—D31:F0)........ 291
DMA Registers............................................................................................. 315
Interrupt Controller I/O Address Map (PIC Registers) ................................. 324
APIC Direct Registers.................................................................................. 331
APIC Indirect Registers ............................................................................... 331
RTC I/O Registers ....................................................................................... 337
RTC (Standard) RAM Bank ......................................................................... 338
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Intel^® 82801DB ICH4 Datasheet