82801DB Datasheet, PDF (373/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.9.5
TCO1_STS—TCO1 Status Register
I/O Address:
Default Value:
Lockable:
TCOBASE +04h
0000h
No
Attribute:
Size:
Power Well:
R/WC, RO
16 bit
Core
(Except bit 7, in RTC)
Bit
15:13
12
11
10
9
8
Description
Reserved
HUBSERR_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Intel^® ICH4 received an SERR# message via the hub interface. The software must read the
memory controller hub (or its equivalent) to determine the reason for the SERR#.
NOTE: If this bit is set AND the SERR_EN bit in CMD register (D30:F0, Offset 04h, bit 8) is also
set, the ICH4 will set the SSE bit in SECSTS register (D30:F0, offset 1Eh, bit 14) AND will
also generate a NMI (or SMI# if NMI routed to SMI#).
HUBNMI_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = ICH4 received an NMI message via the hub interface. The software must read the memory
controller hub (or its equivalent) to determine the reason for the NMI.
HUBSMI_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = ICH4 received an SMI message via the hub interface. The software must read the memory
controller hub (or its equivalent) to determine the reason for the SMI#.
HUBSCI_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = ICH4 received an SCI message via the hub interface. The software must read the memory
controller hub (or its equivalent) to determine the reason for the SCI.
BIOSWR_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = ICH4 sets this bit and generates and SMI# to indicate an illegal attempt to write to the BIOS.
This occurs when either:
• The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or
• Any write is attempted to the BIOS and the BIOSWP bit is also set.
NOTE: On write cycles attempted to the 4-MB lower alias to the BIOS space, the BIOSWR_STS
will not be set.
NEWCENTURY_STS — R/WC. This bit is in the RTC well.
0 = Cleared by writing a 1 to the bit position or by RTCRST# going active.
1 = This bit is set when the Year byte (RTC I/O space, index offset 09h) rolls over from 99 to 00.
Setting this bit will cause an SMI# (but not a wake event).
Note that the NEWCENTURY_STS bit is not valid when the RTC battery is first installed (or when
7
RTC power has not been maintained). Software can determine if RTC power has not been
maintained by checking the RTC_PWR_STS bit, or by other means (e.g., a checksum on RTC
RAM). If RTC power is determined to have not been maintained, BIOS should set the time to a
legal value and then clear the NEWCENTURY_STS bit.
The NEWCENTURY_STS bit may take up to 3 RTC clocks for the bit to be cleared after a 1 is
written to the bit to clear it. After writing a 1 to this bit, software should not exit the SMI handler until
verifying that the bit has actually been cleared. This will ensure that the SMI is not re-entered.
6:4 Reserved
Intel^® 82801DB ICH4 Datasheet
373