82801DB Datasheet, PDF (130/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.11 Processor Interface (D31:F0)
The ICH4 interfaces to the processor with a variety of signals
• Standard Outputs to processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#, IGNNE#,
CPUSLP#
• Standard Input from processor: FERR#
Most ICH4 outputs to the processor use standard buffers. The ICH4 has a separate V_CC signal
which is pulled up at the system level to the processor voltage, and thus determines V_OH for the
outputs to the processor. Note that this is different than previous generations of chips, that have
used open-drain outputs. This new method saves up to 12 external pull-up resistors.
The ICH4 also handles the speed setting for the processor by holding specific signals at certain
states just prior to CPURST going inactive. This avoids the glue often required with other chipsets.
The ICH4 does not support the processor’s FRC mode.
5.11.1 Processor Interface Signals
This section describes each of the signals that interface between the ICH4 and the processor(s).
Note that the behavior of some signals may vary during processor reset, as the signals are used for
frequency strapping.
5.11.1.1
A20M#
The A20M# signal will be active (low) when both of the following conditions are true:
• The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a 0
• The A20GATE input signal is a 0
The A20GATE input signal is expected to be generated by the external microcontroller (KBC).
5.11.1.2
INIT#
The INIT# signal will be active (driven low) based on any one of several events described in
Table 5-30. When any of these events occur, INIT# will be driven low for 16 PCI clocks, then
driven high.
Note: The 16-clock counter for INIT# assertion will halt while STPCLK# is active. Therefore, if INIT# is
supposed to go active while STPCLK# is asserted, it will actually go active after STPCLK# goes
inactive.
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Intel^® 82801DB ICH4 Datasheet