82801DB Datasheet, PDF (300/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.1.19
.
9.1.20
D31_ERR_CFG—Device 31 Error Configuration Register
(LPC I/F—D31:F0)
Offset Address: 88h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8 bit
Core
This register configures the ICH4’s Device 31 responses to various system errors. The actual
assertion of SERR# is enabled via the PCI Command register
Bit
Description
7:3 Reserved
SERR# on Received Target Abort Enable (SERR_RTA_EN) — R/W.
2 0 = Disable. No SERR# assertion on Received Target Abort.
1 = The Intel^® ICH4 will generate SERR# when SERR_RTA is set if SERR_EN is set.
SERR# on Delayed Transaction Timeout Enable (SERR_DTT_EN) — R/W.
1 0 = Disable. No SERR# assertion on Delayed Transaction Timeout.
1 = The ICH4 will generate SERR# when SERR_DTT bit is set if SERR_EN is set.
0 Reserved
D31_ERR_STS—Device 31 Error Status Register
(LPC I/F—D31:F0)
Offset Address: 8Ah
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/WC
8 bit
Core
This register configures the ICH4’s Device 31 responses to various system errors. The actual
assertion of SERR# is enabled via the PCI Command register.
Bit
Description
7:3 Reserved
SERR# Due to Received Target Abort (SERR_RTA) — R/WC.
2
0 = Software clears this bit by writing a 1 to the bit location.
1 = The Intel^® ICH4 sets this bit when it receives a target abort. If SERR_EN, the ICH4 will also
generate an SERR# when SERR_RTA is set.
SERR# Due to Delayed Transaction Timeout (SERR_DTT) — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 _{1 = When a PCI master does not return for the data within 1 ms of the cycle’s completion, the ICH4}
clears the delayed transaction and sets this bit. If both SERR_DTT_EN and SERR_EN are set,
then ICH4 will also generate an SERR# when SERR_DTT is set.
0 Reserved
300
Intel^® 82801DB ICH4 Datasheet