82801DB Datasheet, PDF (474/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

AC ’97 Audio Controller Registers (D31:F5)
14.1.13
MBBAR—Bus Master Base Address Register
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
1C–1Fh
00000000h
No
Attribute:
Size:
Power Well:
R/W, RO
32 bits
Core
This BAR creates 256-bytes of memory space to signify the base address of the bus master
memory space. The lower 64-bytes of the space pointed to by this register point to the same
registers as the MBBAR.
Bit
Description
31:8
Base Address — R/W. I/O offset to use for decoding the PCM In, PCM Out, and Microphone 1
DMA engines.
7:3 Reserved. Read as 0s.
2:1 Type — RO. Indicates the base address exists in 32-bit address space
0
Resource Type Indicator (RTE) — RO. This bit is set to 0, indicating a request for memory space.
14.1.14
SVID—Subsystem Vendor ID Register (Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
2D–2Ch
0000h
No
Attribute:
Size:
Power Well:
R/WO
16 bits
Core
The SVID register, in combination with the Subsystem ID register, enable the operating
environment to distinguish one audio subsystem from the other(s). This register is implemented as
write-once register. Once a value is written to it, the value can be read back. Any subsequent writes
will have no effect.
This register is not affected by the D3_HOT to D0 transition.
Bit
Description
15:0 Subsystem Vendor ID — R/Write-Once.
474
Intel^® 82801DB ICH4 Datasheet