82801DB Datasheet, PDF (456/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

SMBus Controller Registers (D31:F3)
13.2 SMBUS I/O Registers
Table 13-2. SMB I/O Registers
Offset
Mnemonic
Register Name
00h
HST_STS
Host Status
02h
HST_CNT
Host Control
03h
HST_CMD
Host Command
04h
XMIT_SLVA
Transmit Slave Address
05h
HST_D0
Host Data 0
06h
HST_D1
Host Data 1
07h
HOST_BLOCK_DB Host Block Data Byte
08h
PEC
Packet Error Check
09h
RCV_SLVA
Receive Slave Address
0Ah
SLV_DATA
Slave Data
0Ch
AUX_STS
Auxiliary Status
0Dh
AUX_CTL
Auxiliary Control
0Eh
SMLINK_PIN_CTL SMLink Pin Control
0Fh
SMBUS_PIN_CTL SMBus Pin Control
10h
SLV_STS
Slave Status
11h
SLV_CMD
Slave Command
14h
NOTIFY_DADDR Notify Device Address
16h
NOTIFY_DLOW Notify Data Low Byte
17h
NOTIFY_DHIGH Notify Data High Byte
Default
00h
00h
00h
00h
00h
00h
00h
00h
44h
0000h
00h
00h
04h
04h
00h
00h
00h
00h
00h
Type
R/WC,
RO
R/W, WO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/WC
R/W
R/W, RO
R/W, RO
R/WC
R/W
RO
RO
RO
13.2.1
HST_STS—Host Status Register
Register Offset: 00h
Default Value: 00h
Attribute:
Size:
R/WC, RO
8-bits
All status bits are set by hardware and cleared by the software writing a one to the particular bit
position. Writing a zero to any bit position has no effect.
Bit
Description
Byte Done Status (DS) — R/WC. This bit will be set to 1 when the host controller has received a
byte (for Block Read commands) or if it has completed transmission of a byte (for Block Write
commands) when the 32-byte buffer is not being used. Note that this bit will be set, even on the last
byte of the transfer. Software clears the bit by writing a 1 to the bit position. This bit is not set when
transmission is due to the D110 interface heartbeat.
This bit has no meaning for block transfers when the 32-byte buffer is enabled.
7
NOTE: When the last byte of a block message is received, the host controller will set this bit.
However, it will not immediately set the INTR bit (bit 1 in this register). When the interrupt
handler clears the BYTE_DONE_STS bit, the message is considered complete, and the
host controller will then set the INTR bit (and generate another interrupt). Thus, for a block
message of n bytes, the Intel ICH4 will generate n+1 interrupts. The interrupt handler needs
to be implemented to handle these cases.
456
Intel^® 82801DB ICH4 Datasheet