82801DB Datasheet, PDF (561/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Register Index
Register Index
A
Table A-1. Intel^® ICH4 PCI Configuration Registers (Sheet 1 of 10)
Register Name
Offset
Datasheet Location
Vendor Identification
Device Identification
PCI Command
PCI Device Status
Revision Identification
Sub Class Code
Base Class Code
Cache Line Size
Master Latency Timer
Header Type
CSR Memory-Mapped Base Address
CSR I/O-Mapped Base Address
Subsystem Vendor ID
Subsystem ID
Capabilities Pointer
Interrupt Line Register
Interrupt Pin Register
Minimum Grant Register
Maximum Latency Register
LAN Controller (B1:D8:F0)
00–01h
Section 7.1.1, “VID—Vendor ID Register (LAN Controller—B1:D8:F0)” on
page 7-252
02–03h
04–05h
Section 7.1.2, “DID—Device ID Register (LAN Controller—B1:D8:F0)” on
page 7-252
Section 7.1.3, “PCICMD—PCI Command Register (LAN Controller—
B1:D8:F0)” on page 7-253
06–07h
08h
Section 7.1.4, “PCISTS—PCI Status Register (LAN Controller—
B1:D8:F0)” on page 7-254
Section 7.1.5, “REVID—Revision ID Register (LAN Controller—
B1:D8:F0)” on page 7-255
0Ah
Section 7.1.6, “SCC—Sub-Class Code Register (LAN Controller—
B1:D8:F0)” on page 7-255
0Bh
Section 7.1.7, “BCC—Base-Class Code Register (LAN Controller—
B1:D8:F0)” on page 7-255
0Ch
Section 7.1.8, “CLS—Cache Line Size Register (LAN Controller—
B1:D8:F0)” on page 7-255
0Dh
Section 7.1.9, “PMLT—PCI Master Latency Timer Register (LAN
Controller—B1:D8:F0)” on page 7-256
0Eh
Section 7.1.10, “HEADTYP—Header Type Register (LAN Controller—
B1:D8:F0)” on page 7-256
10–13h
Section 7.1.11, “CSR_MEM_BASE CSR — Memory-Mapped Base
Address Register (LAN Controller—B1:D8:F0)” on page 7-256
14–17h
2C–2Dh
Section 7.1.12, “CSR_IO_BASE — CSR I/O-Mapped Base Address
Register (LAN Controller—B1:D8:F0)” on page 7-257
Section 7.1.13, “SVID — Subsystem Vendor ID (LAN Controller—
B1:D8:F0)” on page 7-257
2E–2Fh
Section 7.1.14, “SID — Subsystem ID (LAN Controller—B1:D8:F0)” on
page 7-257
34h
Section 7.1.15, “CAP_PTR — Capabilities Pointer (LAN Controller—
B1:D8:F0)” on page 7-258
3Ch
Section 7.1.16, “INT_LN — Interrupt Line Register (LAN Controller—
B1:D8:F0)” on page 7-258
3Dh
Section 7.1.17, “INT_PN — Interrupt Pin Register (LAN Controller—
B1:D8:F0)” on page 7-258
3Eh
Section 7.1.18, “MIN_GNT — Minimum Grant Register (LAN Controller—
B1:D8:F0)” on page 7-258
3Fh
Section 7.1.19, “MAX_LAT — Maximum Latency Register (LAN
Controller—B1:D8:F0)” on page 7-259
Intel^® 82801DB ICH4 Datasheet
561