82801DB Datasheet, PDF (574/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Register Index
Table A-3. Intel^® ICH4 Variable I/O Registers (Sheet 2 of 6)
Register Name
Offset
Datasheet Location
Monitor SMI Status
Device Activity Status
Device Trap Enable
Bus Address Tracker
Bus Cycle Tracker
40h
Section 9.8.3.13, “MON_SMI—Device Monitor SMI Status and Enable
Register” on page 9-367
44h
Section 9.8.3.14, “DEVACT_STS — Device Activity Status Register” on
page 9-368
48h
Section 9.8.3.15, “DEVTRAP_EN— Device Trap Enable Register” on
page 9-369
4Ch
Section 9.8.3.16, “BUS_ADDR_TRACK— Bus Address Tracker” on
page 9-370
4Eh
Section 9.8.3.17, “BUS_CYC_TRACK— Bus Cycle Tracker” on page 9-370
TCO I/O Registers at TCOBASE + Offset
TCOBASE = PMBASE + 40h
PMBASE is set in Section 9.1.10, “PMBASE—ACPI Base Address (LPC I/F—D31:F0)” on page 9-296
TCO_RLD: TCO Timer Reload
and Current Value
TCO_TMR: TCO Timer Initial
Value
TCO_DAT_IN: TCO Data In
TCO_DAT_OUT: TCO Data Out
TCO1_STS: TCO Status
TCO2_STS: TCO Status
TCO1_CNT: TCO Control
TCO2_CNT: TCO Control
00h
01h
02h
03h
04h–05h
06h–07h
08h–09h
0Ah–0Bh
Section 9.9.1, “TCO1_RLD—TCO Timer Reload and Current Value Register”
on page 9-371
Section 9.9.2, “TCO1_TMR—TCO Timer Initial Value Register” on
page 9-372
Section 9.9.3, “TCO1_DAT_IN—TCO Data In Register” on page 9-372
Section 9.9.4, “TCO1_DAT_OUT—TCO Data Out Register” on page 9-372
Section 9.9.5, “TCO1_STS—TCO1 Status Register” on page 9-373
Section 9.9.6, “TCO2_STS—TCO2 Status Register” on page 9-374
Section 9.9.7, “TCO1_CNT—TCO1 Control Register” on page 9-375
Section 9.9.8, “TCO2_CNT—TCO2 Control Register” on page 9-376
GPIO I/O Registers at GPIOBASE + Offset
GPIOBASE is set in Section 9.1.14, “GPIOBASE—GPIO Base Address (LPC I/F—D31:F0)” on page 9-298
GPIO Use Select
GPIO Input/Output Select
GPIO Level for Input or Output
GPIO Blink Enable
GPIO Signal Invert
00–03h
04–07h
0C–0Fh
18–1Bh
2C–2Fh
Section 9.10.1, “GPIO_USE_SEL—GPIO Use Select Register” on
page 9-378
Section 9.10.2, “GP_IO_SEL—GPIO Input/Output Select Register” on
page 9-379
Section 9.10.3, “GP_LVL—GPIO Level for Input or Output Register” on
page 9-379
Section 9.10.4, “GPO_BLINK—GPO Blink Enable Register” on page 9-380
Section 9.10.5, “GPI_INV—GPIO Signal Invert Register” on page 9-381
574
Intel^® 82801DB ICH4 Datasheet