82801DB Datasheet, PDF (377/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.9.10
9.9.11
TCO_WDSTATUS—TCO2 Control Register
Offset Address:
Default Value:
Power Well:
TCOBASE + 0Eh
00h
Resume
Attribute:
Size:
R/W
8 bits
Bit
Description
Watchdog Status (WDSTATUS) — R/W. The value written to this register will be sent in the Alert
7:0
On LAN message on the SMLINK interface. It can be used by the BIOS or system management
software to indicate more details on the boot progress. This register will be reset to the default of
00h based on RSMRST# (but not PCI reset).
SW_IRQ_GEN—Software IRQ Generation Register
Offset Address:
Default Value:
Power Well:
TCOBASE + 10h
11h
Core
Attribute:
Size:
R/W
8 bits
Bit
Description
7:2 Reserved
IRQ12_CAUSE — R/W. The state of this bit is logically ANDed with the IRQ12 signal as received
1 by the Intel^® ICH4’s SERIRQ logic. This bit must be a 1 (default) if the ICH4 is expected to receive
IRQ12 assertions from a SERIRQ device.
IRQ1_CAUSE — R/W. The state of this bit is logically ANDed with the IRQ1 signal as received by
0 the ICH4’s SERIRQ logic. This bit must be a 1 (default) if the ICH4 is expected to receive IRQ1
assertions from a SERIRQ device.
Intel^® 82801DB ICH4 Datasheet
377