82801DB Datasheet, PDF (282/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.16
SECSTS—Secondary Status Register (HUB-PCI—D30:F0)
Offset Address: 1E–1Fh
Default Value: 0280h
Attribute:
Size:
R/WC
16 bits
For the writable bits in this register, writing a 1 will clear the bit. Writing a 0 to the bit will have no
effect.
Bit
Description
Detected Parity Error (DPE) — R/WC.
15 0 = This bit is cleared by software writing a 1.
1 = Intel^® ICH4 detected a parity error on the PCI bus.
Received System Error (SSE) — R/WC.
14 0 = Software clears this bit by writing a 1 to the bit position.
1 = SERR# assertion is received on PCI.
Received Master Abort (RMA) — R/WC.
13 0 = Software clears this bit by writing a 1 to the bit position.
1 = Hub interface to PCI cycle is master-aborted on PCI.
Received Target Abort (RTA) — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
12 ^{1 = Hub interface to PCI cycle is target-aborted on PCI. For “completion required” cycles from the}
hub interface, this event should also set the Signaled Target Abort in the Primary Status
Register in this device, and the ICH4 must send the “target abort” status back to the hub
interface.
11 Signaled Target Abort (STA) —RO. The ICH4 does not generate target aborts.
DEVSEL# Timing Status (DEV_STS) — RO.
10:9
01h = Medium timing.
Master Data Parity Error Detected (MDPD) — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = The ICH4 sets this bit when all of the following three conditions are met:
8
• The Parity Error Response Enable bit in the Bridge Control Register (bit 0, offset 3Eh) is set
• USB, AC ’97 or IDE is a Master
• PERR# asserts during a write cycle OR a parity error is detected internally during a read
cycle
7
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1 to indicate that the PCI to hub interface
target logic is capable of receiving fast back-to-back cycles.
6 User Definable Features (UDF) — RO. Hardwired to 0.
5 66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
4:0 Reserved
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Intel^® 82801DB ICH4 Datasheet