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82801DB Datasheet, PDF (277/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4) | |||
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Hub Interface to PCI Bridge Registers (D30:F0)
8.1.3
CMDâCommand Register (HUB-PCIâD30:F0)
Offset Address: 04â05h
Default Value: 0001h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:10
9
8
7
6
5
4
3
2
1
0
Reserved
Fast Back to Back Enable (FBE) â RO. Hardwired to 0. The Intel® ICH4 does not support this
capability.
SERR# Enable (SERR_EN) â R/W.
0 = Disable.
1 = Enable the ICH4 to generate an NMI (or SMI# if NMI routed to SMI#) when the D30:F0 SSE bit
(offset 06h, bit 14) is set.
Wait Cycle Control (WCC) â RO. Hardwired to 0.
Parity Error Response (PER) â R/W.
0 = The ICH4 will ignore parity errors on the hub interface.
1 = The ICH4 is allowed to report parity errors detected on the hub interface.
VGA Palette Snoop (VPS) â RO. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) â RO. Hardwired to 0.
Special Cycle Enable (SCE) â RO. Hardwired to 0 by P2P Bridge spec.
Bus Master Enable (BME) â R/W.
0 = Disable
1 = Allows the Hub interface-to-PCI bridge to accept cycles from PCI to run on the hub interface.
NOTES:
1. This bit does not affect the CF8h and CFCh I/O accesses.
2. Cycles that generated from the ICH4âs Device 31 functionality are not blocked by clearing this
bit. (PC/PCI Cascade Mode cycles may be blocked)
Memory Space Enable (MSE) â R/W. The ICH4 provides this bit as read/writable for software
only. However, the ICH4 ignores the programming of this bit, and runs hub interface memory cycles
to PCI.
I/O Space Enable (IOSE) â R/W. The ICH4 provides this bit as read/writable for software only.
However, the ICH4 ignores the programming of this bit and runs hub interface I/O cycles to PCI that
are not intended for USB, IDE, or AC â97.
Intel® 82801DB ICH4 Datasheet
277
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