82801DB Datasheet, PDF (308/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.1.30
9.1.31
GEN1_DEC—LPC I/F Generic Decode Range 1 Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
E4h–E5h
00h
Yes
Attribute:
Size:
Power Well:
R/W
16 bit
Core
Bit
Description
Generic I/O Decode Range 1 Base Address (GEN1_BASE) — R/W. This address is aligned on a
15:7
128-byte boundary, and must have address lines 31:16 as 0.
NOTE: This generic decode is for I/O addresses only, not memory addresses. The size of this
range is 128 bytes.
6:1 Reserved
Generic Decode Range 1 Enable (GEN1_EN) — R/W.
0 0 = Disable.
1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F
LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
E6h–E7h
00h
Yes
Attribute:
Size:
Power Well:
R/W
16 bit
Core
Bit
Description
15:14
13
12
11
10
9
8
Reserved
CNF2_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This range is used
for a microcontroller.
CNF1_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This range is used
for Super I/O devices.
MC_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This range is used
for a microcontroller.
KBC_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This range is used
for a microcontroller.
GAMEH_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This range is
used for a gameport.
GAMEL_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This range is
used for a gameport.
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Intel^® 82801DB ICH4 Datasheet