82801DB Datasheet, PDF (375/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.9.7
TCO1_CNT—TCO1 Control Register
I/O Address:
Default Value:
Lockable:
TCOBASE +08h
0000h
No
Attribute:
Size:
Power Well:
R/W, R/WC, R/W-Special
16 bit
Core
Bit
15:12
11
10
Description
Reserved
TCO Timer Halt (TCO_TMR_HLT) — R/W.
0 = The TCO Timer is enabled to count.
1 = The TCO Timer will halt. It will not count, and thus cannot reach a value that will cause an SMI#
or set the SECOND_TO_STS bit. When set, this bit will prevent rebooting and prevent Alert On
LAN event messages from being transmitted on the SMLINK (but not Alert On LAN* heartbeat
messages).
SEND_NOW — R/W-Special.
0 = The Intel^® ICH4 will clear this bit when it has completed sending the message. Software must
not set this bit to 1 again until the ICH4 has set it back to 0.
1 = Writing a 1 to this bit will cause the ICH to send an Alert On LAN Event message over the
SMLINK interface, with the Software Event bit set.
NOTE: Setting the SEND_NOW bit causes the ICH4 integrated LAN controller to reset, which can
have unpredictable side-effects. Unless software protects against these side effects,
software should not attempt to set this bit.
NMI2SMI_EN — R/W.
0 = Normal NMI functionality.
1 = Forces all NMIs to instead cause SMIs. The functionality of this bit is dependent upon the
settings of the NMI_EN bit and the GBL_SMI_EN bit as detailed in the following table:
9
NMI_EN GBL_SMI_EN Description
0
0
No SMI# at all because GBL_SMI_EN = 0
0
1
SMI# will be caused due to NMI events
1
0
No SMI# at all because GBL_SMI_EN = 0
1
1
No SMI# due to NMI because NMI_EN = 1
NMI_NOW — R/WC.
0 = This bit is cleared by writing a 1 to the bit position. The NMI handler is expected to clear this bit.
8
Another NMI will not be generated until the bit is cleared.
1 = Writing a 1 to this bit causes an NMI. This allows the BIOS or SMI handler to force an entry to
the NMI handler.
7:0 Reserved
Intel^® 82801DB ICH4 Datasheet
375