82801DB Datasheet, PDF (562/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Register Index
Table A-1. Intel^® ICH4 PCI Configuration Registers (Sheet 2 of 10)
Register Name
Capability ID Register
Next Item Pointer
Power Management Capabilities
Power Management Control/Status
Register
Data Register
Vendor ID
Device ID
PCI Device Command Register
PCI Device Status Register
Revision ID
Sub Class Code
Base Class Code
Primary Master Latency Timer
Header Type
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Secondary Master Latency Timer
IO Base Register
IO Limit Register
Secondary Status Register
Memory Base
Memory Limit
Offset
Datasheet Location
DCh
DDh
DE–DFh
E0–E1h
E2h
Section 7.1.20, “CAP_ID — Capability ID Register (LAN Controller—
B1:D8:F0)” on page 7-259
Section 7.1.21, “NXT_PTR — Next Item Pointer (LAN Controller—
B1:D8:F0)” on page 7-259
Section 7.1.22, “PM_CAP — Power Management Capabilities (LAN
Controller—B1:D8:F0)” on page 7-260
Section 7.1.23, “PMCSR — Power Management Control/Status Register
(LAN Controller—B1:D8:F0)” on page 7-260
Section 7.1.24, “PCIDATA — PCI Power Management Data Register (LAN
Controller—B1:D8:F0)” on page 7-261
Hub Interface to PCI Bridge D30:F0
00–01h
02–03h
04–05h
06–07h
08h
0Ah
0Bh
0Dh
0Eh
18h
19h
1Ah
1Bh
1Ch
1Dh
1E–1Fh
20–21h
22–23h
Section 8.1.1, “VID—Vendor ID Register (HUB-PCI—D30:F0)” on
page 8-276
Section 8.1.2, “DID—Device ID Register (HUB-PCI—D30:F0)” on
page 8-276
Section 8.1.3, “CMD—Command Register (HUB-PCI—D30:F0)” on
page 8-277
Section 8.1.4, “PD_STS—Primary Device Status Register (HUB-PCI—
D30:F0)” on page 8-278
Section 8.1.5, “RID—Revision Identification Register (HUB-PCI—D30:F0)”
on page 8-279
Section 8.1.6, “SCC—Sub-Class Code Register (HUB-PCI—D30:F0)” on
page 8-279
Section 8.1.7, “BCC—Base-Class Code Register (HUB-PCI—D30:F0)” on
page 8-279
Section 8.1.8, “PMLT—Primary Master Latency Timer Register (HUB-
PCI—D30:F0)” on page 8-279
Section 8.1.9, “HEADTYP—Header Type Register (HUB-PCI—D30:F0)”
on page 8-280
Section 8.1.10, “PBUS_NUM—Primary Bus Number Register (HUB-PCI—
D30:F0)” on page 8-280
Section 8.1.11, “SBUS_NUM—Secondary Bus Number Register (HUB-
PCI—D30:F0)” on page 8-280
Section 8.1.12, “SUB_BUS_NUM—Subordinate Bus Number Register
(HUB-PCI—D30:F0)” on page 8-280
Section 8.1.13, “SMLT—Secondary Master Latency Timer Register (HUB-
PCI—D30:F0)” on page 8-281
Section 8.1.14, “IOBASE—I/O Base Register (HUB-PCI—D30:F0)” on
page 8-281
Section 8.1.15, “IOLIM—I/O Limit Register (HUB-PCI—D30:F0)” on
page 8-281
Section 8.1.16, “SECSTS—Secondary Status Register (HUB-PCI—
D30:F0)” on page 8-282
Section 8.1.17, “MEMBASE—Memory Base Register (HUB-PCI—
D30:F0)” on page 8-283
Section 8.1.18, “MEMLIM—Memory Limit Register (HUB-PCI—D30:F0)”
on page 8-283
562
Intel^® 82801DB ICH4 Datasheet