82801DB Datasheet, PDF (564/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Register Index
Table A-1. Intel^® ICH4 PCI Configuration Registers (Sheet 4 of 10)
Register Name
ACPI Control
BIOS Control Register
TCO Control
GPIO Base Address Register
GPIO Control Register
PIRQ[A:D] Routing Control
Serial IRQ Control Register
PIRQ[E:H] Routing Control
Device 31 Error Config Register
Device 31 Error Status Register
PCI DMA Configuration Registers
General Control
General Status
Backed Up Control
Real Time Clock Configuration
LPC COM Port Decode Ranges
LPC FDD & LPT Decode Ranges
LPC Sound Decode Ranges
FWH Decode Enable 1 Register
LPC Generic Decode Range 1
LPC Enables
FWH Select 1 Register
LPC Generic Decode Range 2
Offset
Datasheet Location
44h
Section 9.1.11, “ACPI_CNTL—ACPI Control (LPC I/F — D31:F0)” on
page 9-296
4E–4Fh
54h
Section 9.1.12, “BIOS_CNTL—BIOS Control Register (LPC I/F—D31:F0)”
on page 9-297
Section 9.1.13, “TCO_CNTL — TCO Control (LPC I/F — D31:F0)” on
page 9-297
58–5Bh
Section 9.1.14, “GPIOBASE—GPIO Base Address (LPC I/F—D31:F0)” on
page 9-298
5Ch
60–63h
Section 9.1.15, “GPIO_CNTL—GPIO Control (LPC I/F—D31:F0)” on
page 9-298
Section 9.1.16, “PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control (LPC I/
F—D31:F0)” on page 9-298
64h
68–6Bh
Section 9.1.17, “SERIRQ_CNTL—Serial IRQ Control (LPC I/F—D31:F0)”
on page 9-299
Section 9.1.18, “PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control (LPC I/
F—D31:F0)” on page 9-299
88h
Section 9.1.19, “D31_ERR_CFG—Device 31 Error Configuration Register
(LPC I/F—D31:F0)” on page 9-300
8Ah
90–91h
Section 9.1.20, “D31_ERR_STS—Device 31 Error Status Register (LPC I/
F—D31:F0)” on page 9-300
Section 9.1.21, “PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—
D31:F0)” on page 9-301
D0h–D3h
Section 9.1.22, “GEN_CNTL — General Control Register (LPC I/F —
D31:F0)” on page 9-302
D4h
Section 9.1.23, “GEN_STA—General Status Register (LPC I/F—D31:F0)”
on page 9-304
D5h
Section 9.1.24, “BACK_CNTL—Backed Up Control Register (LPC I/F—
D31:F0)” on page 9-304
D8h
Section 9.1.25, “RTC_CONF—RTC Configuration Register (LPC I/F—
D31:F0)” on page 9-305
E0h
Section 9.1.26, “COM_DEC—LPC I/F Communication Port Decode
Ranges (LPC I/F—D31:F0)” on page 9-305
E1h
Section 9.1.27, “FDD/LPT_DEC—LPC I/F FDD & LPT Decode Ranges
(LPC I/F—D31:F0)” on page 9-306
E2h
Section 9.1.28, “SND_DEC—LPC I/F Sound Decode Ranges (LPC I/F—
D31:F0)” on page 9-306
E3h
Section 9.1.29, “FWH_DEC_EN1—FWH Decode Enable 1 Register (LPC
I/F—D31:F0)” on page 9-307
E4h–E5h
Section 9.1.30, “GEN1_DEC—LPC I/F Generic Decode Range 1 Register
(LPC I/F—D31:F0)” on page 9-308
E6h–E7h
Section 9.1.31, “LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)”
on page 9-308
E8h
Section 9.1.32, “FWH_SEL1—FWH Select 1 Register (LPC I/F—D31:F0)”
on page 9-310
ECh–EDh
Section 9.1.33, “GEN2_DEC—LPC I/F Generic Decode Range 2 Register
(LPC I/F—D31:F0)” on page 9-311
564
Intel^® 82801DB ICH4 Datasheet