82801DB Datasheet, PDF (134/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.11.3 Speed Strapping for Processor
The ICH4 directly sets the speed straps for the processor, saving the external logic that has been
needed with prior PCIsets. Refer to processor specification for speed strapping definition.
The ICH4 performs the following to set the speed straps for the processor:
1. While PCIRST# is active, the ICH4 drives A20M#, IGNNE#, NMI, and INTR high.
2. As soon as PWROK goes active, the ICH4 reads the FREQ_STRAP field contents.
3. The next step depends on the power state being exited as described in Table 5-33.
Table 5-33. Frequency Strap Behavior Based on Exit State
State
Exiting
ICH4
S1
There is no processor reset, so no frequency strap logic is used.
S3, S4, S5,
or G3
Based on PWROK going active, the ICH4 will deassert PCIRST#, and based on the value of the
FREQ_STRAP field (D31:F0,Offset D4), the Intel^® ICH4 will drive the intended core frequency
values on A20M#, IGNNE#, NMI, and INTR. The ICH4 will hold these signals for 120 ns after
CPURST# is deasserted by the Host controller.
Table 5-34. Frequency Strap Bit Mapping
FREQ_STRAP Bits [3:0]
3
2
1
0
Sets High/Low Level for the Corresponding Signal
NMI
INTR
IGNNE#
A20M#
NOTE: The FREQ_STRAP register is in the RTC well. The value in the register can be forced to 1111h via a
pinstrap (AC_SDOUT signal), or the ICH4 can automatically force the speed strapping to 1111h if the
processor fails to boot.
Figure 5-13. Signal Strapping
Processor
CPURST#
Host Controller
A20M#, IGNNE#,
INTR, NMI
INIT#
ICH4
PCIRST#
4x 2 to 1
Mux
Frequency
Strap Register
PWROK
134
Intel^® 82801DB ICH4 Datasheet