82801DB Datasheet, PDF (132/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.11.1.4 NMI
Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in Table 5-31.
Table 5-31. NMI Sources
Cause of NMI
Comment
SERR# goes active (either internally, externally Can instead be routed to generate an SCI, through the
via SERR# signal, or via message from the MCH) NMI2SCI_EN bit (Device 31:Function 0, offset 4E, bit 11).
IOCHK# goes active via SERIRQ# stream
(ISA system Error)
Can instead be routed to generate an SCI, through the
NMI2SCI_EN bit (Device 31:Function 0, offset 4E, bit 11).
5.11.1.5
STPCLK# and CPUSLP# Signals
The ICH4 power management logic controls these active-low signals. Refer to Section 5.12 for
more information on the functionality of these signals.
5.11.1.6
CPUPWRGOOD Signal
This signal is connected to the processor’s PWRGOOD input. This is an open-drain output signal
(external pull-up resistor required) that represents a logical AND of the ICH4’s PWROK and
VRMPWRGD signals.
5.11.2 Dual-Processor Designs
5.11.2.1 Signal Differences
In dual-processor (DP) designs, some of the processor signals are unused or used differently than
for uniprocessor designs.
Table 5-32. DP Signal Differences
Signal
A20M# / A20GATE
STPCLK#
FERR# / IGNNE#
Difference
Generally not used, but still supported by Intel^® ICH4.
Used for S1 State as well as preparation for entry to S3–S5
Also allows for THERM# based throttling (not via ACPI control methods).
Should be connected to both processors.
Generally not used, but still supported by ICH4.
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Intel^® 82801DB ICH4 Datasheet