82801DB Datasheet, PDF (273/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LAN Controller Registers (B1:D8:F0)
7.2.13 Statistical Counters
The ICH4’s integrated LAN controller provides information for network management statistics by
providing on-chip statistical counters that count a variety of events associated with both transmit
and receive. The counters are updated by the LAN controller when it completes the processing of a
frame (that is, when it has completed transmitting a frame on the link or when it has completed
receiving a frame). The Statistical Counters are reported to the software on demand by issuing the
Dump Statistical Counters command or Dump and Reset Statistical Counters command in the SCB
Command Unit Command (CUC) field.
Table 7-6. Statistical Counters (Sheet 1 of 2)
ID
Counter
Description
0 Transmit Good Frames
This counter contains the number of frames that were transmitted
properly on the link. It is updated only after the actual transmission
on the link is completed, not when the frame was read from memory
as is done for the Transmit Command Block status.
4
Transmit Maximum
Collisions (MAXCOL) Errors
This counter contains the number of frames that were not transmitted
because they encountered the configured maximum number of
collisions.
8
Transmit Late Collisions
(LATECOL) Errors
This counter contains the number of frames that were not transmitted
since they encountered a collision later than the configured slot time.
12 Transmit Underrun Errors
A transmit underrun occurs because the system bus cannot keep up
with the transmission. This counter contains the number of frames
that were either not transmitted or retransmitted due to a transmit
DMA underrun. If the LAN controller is configured to retransmit on
underrun, this counter may be updated multiple times for a single
frame.
16
Transmit Lost Carrier Sense
(CRS)
This counter contains the number of frames that were transmitted by
the LAN controller despite the fact that it detected the deassertion of
CRS during the transmission.
20 Transmit Deferred
This counter contains the number of frames that were deferred
before transmission due to activity on the link.
24 Transmit Single Collisions
This counter contains the number of transmitted frames that
encountered one collision.
28
Transmit Multiple Collisions
This counter contains the number of transmitted frames that
encountered more than one collision.
32 Transmit Total Collisions
This counter contains the total number of collisions that were
encountered while attempting to transmit. This count includes late
collisions and frames that encountered MAXCOL.
36 Receive Good Frames
This counter contains the number of frames that were received
properly from the link. It is updated only after the actual reception
from the link is completed and all the data bytes are stored in
memory.
40 Receive CRC Errors
This counter contains the number of aligned frames discarded
because of a CRC error. This counter is updated, if needed,
regardless of the Receive Unit state. The Receive CRC Errors
counter is mutually exclusive of the Receive Alignment Errors and
Receive Short Frame Errors counters.
44 Receive Alignment Errors
This counter contains the number of frames that are both misaligned
(for example, CRS deasserts on a non-octal boundary) and contain a
CRC error. The counter is updated, if needed, regardless of the
Receive Unit state. The Receive Alignment Errors counter is
mutually exclusive of the Receive CRC Errors and Receive Short
Frame Errors counters.
Intel^® 82801DB ICH4 Datasheet
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