82801DB Datasheet, PDF (553/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Testability
Likewise, applying Vector 7 (all 1s) to the chain inputs (given that there are an even number of
input signals in the chain), will consistently produce a 1 at the XOR chain output on a good board.
One short to VSS (or open floating to VSS) will result in a 0 at the chain output, signaling a defect.
It is important to note that the number of inputs pulled to 1 will affect the expected chain output
value. If the number of chain inputs pulled to 1 is even, then expect 1 at the output. If the number of
chain inputs pulled to 1 is odd, expect 0 at the output.
Continuing with the example in Table 19-2, as the input pins are driven to 1 across the chain in
sequence, the XOR Output will toggle between 0 and 1. Any break in the toggling sequence
(e.g., 1011) will identify the location of the short or open.
Table 19-3. XOR Chain 1
Pin Name
AC_SYNC
AC_SDOUT
PIRQE#/GPIO2
GNT2#
GNT3#
GNTA#/GPIO16
REQB#/REQ5#/
GPIO1
REQ4#
REQA#/GPIO0
PIRQF#/GPIO3
GNT4#
GNTB#/
GNT5#GPIO17
GNT1#
PIRQC#
PIRQA#
PIRQH#/GPIO5
PIRQD#
REQ1#
REQ2#
AD18
REQ0#
PIRQG#/GPIO4
AD28
PIRQB#
AD15
Ball #
C9
D9
C8
A7
B7
E8
Notes
Top of XOR Chain
2nd signal in XOR
A6
B6
B5
D7
D6
C5
E6
B4
D5
C4
A3
A2
B3
E5
B1
C3
D3
C2
F5
Pin Name
GNT0#
AD22
AD30
AD20
AD16
AD4
AD24
AD0
STOP#
AD11
AD26
AD6
TRDY#
FRAME#
AD9
AD2
PAR
AD5
AD13
AD1
SERR#
C/BE0#
C/BE1#
AD3
AD10
TP[0]
Ball #
C1
E4
D2
E3
F4
G5
E2
H5
F3
G4
E1
H4
F2
F1
G2
H3
G1
J4
H2
J3
K5
J2
K4
K1
L1
AB2
Notes⁽¹⁾
XOR Chain 1
OUTPUT
NOTES:
1. RTCRST# asserted for 4 PCI clocks while PWROK active.
Intel^® 82801DB ICH4 Datasheet
553