82801DB Datasheet, PDF (336/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
Bit
Description
Delivery Status — RO. This field contains the current status of the delivery of this interrupt.
Writes to this bit have no effect.
12
0 = Idle. No activity for this interrupt.
1 = Pending. Interrupt has been injected, but delivery is held up due to the APIC bus being busy
or the inability of the receiving APIC unit to accept the interrupt at this time.
Destination Mode — R/W. This field determines the interpretation of the Destination field.
11
0 = Physical. Destination APIC ID is identified by bits [59:56].
1 = Logical. Destinations are identified by matching bit [63:56] with the Logical Destination in the
Destination Format Register and Logical Destination Register in each Local APIC.
Delivery Mode — R/W. This field specifies how the APICs listed in the destination field should act
10:8 upon reception of this signal. Certain Delivery Modes will only operate as intended when used in
conjunction with a specific trigger mode. These encodings are listed in the note below:
7:0
Vector — R/W. This field contains the interrupt vector for this interrupt. Values range between 10h
and FEh.
NOTE: Delivery Mode Encoding (Bits 10:8):
000 = Fixed. Deliver the signal on the INTR signal of all processor cores listed in the destination.
Trigger Mode can be edge or level.
001 = Lowest Priority. Deliver the signal on the INTR signal of the processor core that is executing at
the lowest priority among all the processors listed in the specified destination. Trigger Mode can
be edge or level.
010 = SMI (System Management Interrupt). Requires the interrupt to be programmed as edge
triggered. The vector information is ignored but must be programmed to all zeroes for future
compatibility. Not supported
011 = Reserved
100 = NMI. Deliver the signal on the NMI signal of all processor cores listed in the destination. Vector
information is ignored. NMI is treated as an edge triggered interrupt even if it is programmed as
level triggered. For proper operation this redirection table entry must be programmed to edge
triggered. The NMI delivery mode does not set the RIRR bit. Once the interrupt is detected, it will
be sent over the APIC bus. If the redirection table is incorrectly set to level, the loop count will
continue counting through the redirection table addresses. Once the count for the NMI pin is
reached again, the interrupt will be sent over the APIC bus again. Not supported
101 = INIT. Deliver the signal to all processor cores listed in the destination by asserting the INIT signal.
All addressed local APICs will assume their INIT state. INIT is always treated as an edge
triggered interrupt even if programmed as level triggered. For proper operation this redirection
table entry must be programmed to edge triggered. The INIT delivery mode does not set the
RIRR bit. Once the interrupt is detected, it will be sent over the APIC bus. If the redirection table
is incorrectly set to level, the loop count will continue counting through the redirection table
addresses. Once the count for the INIT pin is reached again, the interrupt will be sent over the
APIC bus again. Not supported
110 = Reserved
111 = ExtINT. Deliver the signal to the INTR signal of all processor cores listed in the destination as an
interrupt that originated in an externally connected 8259A compatible interrupt controller. The
INTA cycle that corresponds to this ExtINT delivery will be routed to the external controller that is
expected to supply the vector. Requires the interrupt to be programmed as edge triggered.
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Intel^® 82801DB ICH4 Datasheet