82801DB Datasheet, PDF (8/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

5.17.3 USB 2.0 Enhanced Host Controller DMA ....................................... 196
5.17.4 Data Encoding and Bit Stuffing....................................................... 199
5.17.5 Packet Formats............................................................................... 199
5.17.6 USB EHCI Interrupts and Error Conditions..................................... 200
5.17.7 USB EHCI Power Management...................................................... 201
5.17.8 Interaction with Classic Host Controllers ........................................ 202
5.17.9 USB 2.0 Legacy Keyboard Operation............................................. 204
5.17.10 USB 2.0 EHCI Based Debug Port .................................................. 205
5.18 SMBus Controller Functional Description (D31:F3) ..................................... 210
5.18.1 Host Controller ................................................................................ 210
5.18.2 Bus Arbitration ................................................................................ 220
5.18.3 Bus Timing...................................................................................... 220
5.18.4 Interrupts / SMI# ............................................................................. 221
5.18.5 SMBALERT# .................................................................................. 222
5.18.6 SMBus CRC Generation and Checking.......................................... 222
5.18.7 SMBus Slave Interface ................................................................... 222
5.19 AC ’97 Controller Functional Description (Audio D31:F5, Modem D31:F6). 227
5.19.1 PCI Power Management................................................................. 229
5.19.2 AC-Link Overview ........................................................................... 230
5.19.3 AC-Link Low Power Mode .............................................................. 238
5.19.4 AC ’97 Cold Reset .......................................................................... 239
5.19.5 AC ’97 Warm Reset ........................................................................ 239
5.19.6 System Reset ................................................................................. 240
5.19.7 Hardware Assist to Determine AC_SDIN Used Per Codec ............ 241
5.19.8 Software Mapping of AC_SDIN to DMA Engine ............................. 241
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Register and Memory Mapping ................................................................... 243
6.1 PCI Devices and Functions ......................................................................... 244
6.2 PCI Configuration Map ................................................................................ 245
6.3 I/O Map ........................................................................................................ 245
6.3.1 Fixed I/O Address Ranges.............................................................. 245
6.3.2 Variable I/O Decode Ranges .......................................................... 248
6.4 Memory Map................................................................................................ 249
6.4.1 Boot-Block Update Scheme............................................................ 250
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LAN Controller Registers (B1:D8:F0) ....................................................... 251
7.1 PCI Configuration Registers (B1:D8:F0)...................................................... 251
7.1.1 VID—Vendor ID Register (LAN Controller—B1:D8:F0) .................. 252
7.1.2 DID—Device ID Register (LAN Controller—B1:D8:F0) .................. 252
7.1.3 PCICMD—PCI Command Register (LAN Controller—B1:D8:F0) .. 253
7.1.4 PCISTS—PCI Status Register (LAN Controller—B1:D8:F0) .......... 254
7.1.5 REVID—Revision ID Register (LAN Controller—B1:D8:F0)........... 255
7.1.6 SCC—Sub-Class Code Register (LAN Controller—B1:D8:F0) ...... 255
7.1.7 BCC—Base-Class Code Register (LAN Controller—B1:D8:F0)..... 255
7.1.8 CLS—Cache Line Size Register (LAN Controller—B1:D8:F0) ....... 255
7.1.9 PMLT—PCI Master Latency Timer Register
(LAN Controller—B1:D8:F0) ........................................................... 256
7.1.10 HEADTYP—Header Type Register (LAN Controller—B1:D8:F0) .. 256
7.1.11 CSR_MEM_BASE CSR — Memory-Mapped Base Address
Register (LAN Controller—B1:D8:F0)............................................. 256
7.1.12 CSR_IO_BASE — CSR I/O-Mapped Base Address Register
(LAN Controller—B1:D8:F0) ........................................................... 257
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Intel^® 82801DB ICH4 Datasheet