82801DB Datasheet, PDF (226/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
Table 5-97. Data Values for Slave Read Registers (Sheet 2 of 2)
Register Bits
Description
4
3
This bit will be set after the TCO timer times out a second time (Both TIMEOUT and
SECOND_TO_STS bits set).
4
6:4 Reserved.
The bit will reflect the state of the GPI[11]/SMBALERT# signal, and will depend on the
GP_INV[11] bit. It does not matter if the pin is configured as GPI[11] or SMBALERT#.
4
7
• If the GP_INV[11] bit is 1 then the value of register 4 bit 7 will equal the level of the
GPI[11]/SMBALERT# pin (high = 1, low = 0).
• If the GP_INV[11] bit is 0 then the value of register 4 bit 7 will equal the inverse of the
level of the GPI[11]/SMBALERT# pin (high = 1, low = 0).
5
0
Unprogrammed FWH bit. This bit will be 1 to indicate that the first BIOS fetch returned FFh,
which indicates that the FWH is probably blank.
5
1 Reserved
5
2
CPU Power Failure Status: 1 if the CPUPWR_FLR bit in the GEN_PMCON_2 register is
set.
5
7:3 Reserved
6
7:0 Contents of the Message 1 register. See Section 9.9.9.
7
8
9–FFh
7:0 Contents of the Message 2 register. See Section 9.9.9.
7:0 Contents of the WDSTATUS register. See Section 9.9.10.
7:0 Reserved
5.18.7.2.1 Behavioral Notes
According to SMBus protocol, Read and Write messages always begin with a Start bit–Address–
Write bit sequence. When the ICH4 detects that the address matches the value in the Receive Slave
Address register, it will assume that the protocol is always followed and ignore the Write bit (bit 9)
and signal an Acknowledge during bit 10 (See Table 5-93 and Table 5-96). In other words, if a
Start–Address–Read occurs (which is illegal for SMBus Read or Write protocol) and the address
matches the ICH4’s Slave Address, the ICH4 will still grab the cycle.
Also according to SMBus protocol, a Read cycle contains a Repeated Start–Address–Read
sequence beginning at bit 20 (See Table 5-96). Once again, if the Address matches the ICH4’s
Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and proceed with
the Slave Read cycle.
Note: An external microcontroller must not attempt to access the ICH4’s SMBus Slave logic until at least
1 second after both RTCRST# and RSMRST# are deasserted (high).
5.18.7.3 Format of Host Notify Command
The ICH4 tracks and responds to the standard Host Notify command as specified in the SMBus 2.0
specification. The host address for this command is fixed to 0001000b. If the ICH4 already has
data for a previously-received host notify command which has not been serviced yet by the host
software (as indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host
address byte of the protocol. This allows the host to communicate non-acceptance to the master and
retain the host notify address and data values for the previous cycle until host software completely
services the interrupt. Table 5-98 shows the Host Notify format.
Note: Host software must always clear the HOST_NOTIFY_STS bit after completing any necessary
reads of the address and data registers.
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Intel^® 82801DB ICH4 Datasheet