82801DB Datasheet, PDF (309/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
Bit
Description
ADLIB_LPC_EN — R/W.
7 0 = Disable.
1 = Enables the decoding of the I/O locations 388h–38Bh to the LPC interface.
MSS_LPC_EN — R/W.
6
0 = Disable.
1 = Enables the decoding of the MSS range to the LPC interface. This range is selected in the
LPC_Sound Decode Range Register.
MIDI_LPC_EN — R/W.
5
0 = Disable.
1 = Enables the decoding of the MIDI range to the LPC interface. This range is selected in the
LPC_Sound Decode Range Register.
SB16_LPC_EN — R/W.
4
0 = Disable.
1 = Enables the decoding of the SB16 range to the LPC interface. This range is selected in the
LPC_Sound Decode Range Register.
FDD_LPC_EN — R/W.
3
0 = Disable.
1 = Enables the decoding of the FDD range to the LPC interface. This range is selected in the
LPC_FDD/LPT Decode Range Register.
LPT_LPC_EN — R/W.
2
0 = Disable.
1 = Enables the decoding of the LPTrange to the LPC interface. This range is selected in the
LPC_FDD/LPT Decode Range Register.
COMB_LPC_EN — R/W.
1
0 = Disable.
1 = Enables the decoding of the COMB range to the LPC interface. This range is selected in the
LPC_COM Decode Range Register.
COMA_LPC_EN — R/W.
0
0 = Disable.
1 = Enables the decoding of the COMA range to the LPC interface. This range is selected in the
LPC_COM Decode Range Register.
Intel^® 82801DB ICH4 Datasheet
309