82801DB Datasheet, PDF (383/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

IDE Controller Registers (D31:F1)
IDE Controller Registers (D31:F1) 10
10.1 PCI Configuration Registers (IDE—D31:F1)
Note: Registers that are not shown should be treated as Reserved (See Section 6.2 for details).
All of the IDE registers are in the core well. None can be locked.
Table 10-1. PCI Configuration Register Address Map (IDE—D31:F1)
Offset
00–01h
02–03h
04–05h
06–07h
08h
09h
0Ah
0Bh
0Dh
0Eh
10–13h
14–17h
18–1Bh
1C–1Fh
20–23h
24–27h
2C–2Dh
2E–2Fh
3C
3D
40–41h
42–43h
44h
48h
4A–4Bh
54h
Mnemonic
VID
DID
CMD
STS
RID
PI
SCC
BCC
MLT
HTYPE
PCMD_BAR
PCNL_BAR
SCMD_BAR
SCNL_BAR
BAR
EXBAR
SVID
SID
INTR_LN
INTR_PN
IDE_TIMP
ID_TIMS
SIDETIM
SDMAC
SDMATIM
IDE_CONFIG
Register Name
Vendor ID
Device ID
Command Register
Device Status
Revision ID
Programming Interface
Sub Class Code
Base Class Code
Master Latency Timer (Note 1)
Header Type
Primary Command Block Base Address
Primary Control Block Base Address
Secondary Command Block Base
Address
Secondary Control Block Base Address
Base Address Register
Expansion BAR
Subsystem Vendor ID
Subsystem ID
Interrupt Line
Interrupt Pin
Primary IDE Timing
Secondary IDE Timing
Slave IDE Timing
Synchronous DMA Control Register
Synchronous DMA Timing Register
IDE I/O Configuration Register
Default
8086h
24CBh
00h
0280h
See Note 2
8Ah
01h
01h
00
00h
00000001h
00000001h
00000001h
00000001h
00000001h
00h
00
00
00
01
0000h
0000h
00h
00h
0000h
00h
Type
RO
RO
R/W, RO
R/WC, RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/WO
R/WO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NOTES:
1. The ICH4 IDE controller is not arbitrated as a PCI device, therefore it does not need a master latency timer.
2. Refer to the ICH4 Specification Update for the value of the Revision ID Register.
Intel^® 82801DB ICH4 Datasheet
383