82801DB Datasheet, PDF (535/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Electrical Characteristics
Table 17-14. IOAPIC Bus Timing
Sym
t120
t121
t122
Parameter
APICCD[1:0]# Valid Delay from APICCLK Rising
APICCD[1:0]# Setup Time to APICCLK Rising
APICCD[1:0]# Hold Time from APICCLK Rising
Min Max Units Notes Fig
3.0 12.0 ns
17-3
8.5
ns
17-4
3.0
ns
17-4
NOTE: The Min AC column indicates the minimum times required by the SMBus and/or I²C specifications. The
ICH4 tolerates these timings on both its SMBus and SMLink interfaces.
Table 17-15. SMBus Timing
Sym
Parameter
t130 Bus Tree Time Between Stop and Start Condition
t131
Hold Time after (repeated) Start Condition. After this
period, the first clock is generated.
t132 Repeated Start Condition Setup Time
t133 Stop Condition Setup Time
t134 Data Hold Time
t135 Data Setup Time
t136 Device Time Out
t137 Cumulative Clock Low Extend Time (slave device)
t138 Cumulative Clock Low Extend Time (master device)
Min Max Units Notes Fig
4.7
µs
17-17
4.0
µs
17-17
4.7
µs
4.0
µs
0
ns 4
250
ns
25
35 ms 1
25 ms 2
10 ms 3
17-17
17-17
17-17
17-17
17-17
17-17
NOTES:
1. A device will timeout when any clock low exceeds this value.
2. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the
initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines
and reset itself.
3. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a
message as defined from start-to-ack, ack-to-ack or ack-to-stop.
4. t134 has a minimum timing for I²C of 0 ns, while the minimum timing for SMBus is 300 ns.
Table 17-16. AC ’97 Timing
Sym
Parameter
t140 ACSDIN[2:0] Setup to Falling Edge of BITCLK
t141 ACSDIN[2:0] Hold from Falling Edge of BITCLK
t142
ACSYNC, ACSDOUT valid delay from rising edge of
BITCLK
Min Max Units Notes Fig
10
ns
17-23
10
ns
17-23
15
ns
17-23
Intel^® 82801DB ICH4 Datasheet
535