82801DB Datasheet, PDF (446/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

EHCI Controller Registers (D29:F7)
Bit
Description
Force Port Resume — RW. Software sets this bit to a 1 to drive resume signaling. The Host
controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state.
When this bit transitions to a 1 because a J-to-K transition is detected, the Port Change Detect bit in
the EHCI_STS register is also set to a 1. If software sets this bit to a 1, the host controller must not
set the Port Change Detect bit.
0 = No resume (K-state) detected/driven on port. (Default).
6 ^{1 = Resume detected/driven on port.}
NOTE: When the EHCI controller owns the port, the resume sequence follows the defined
sequence documented in the Universal Serial Bus (USB) Specification, Revision 2.0. The
resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a 1.
Software must appropriately time the Resume and set this bit to a 0 when the appropriate
amount of time has elapsed. Writing a 0 (from 1) causes the port to return to high-speed
mode (forcing the bus below the port into a high-speed idle). This bit will remain 1 until the
port has switched to the high-speed idle.
Overcurrent Change— R/WC. Default = 0. The functionality of this bit is not dependent upon the
port owner.
5 _{0 = Software clears this bit by writing a 1 to this bit position.}
1 = There is a change to Over-current Active.
Overcurrent Active — RO. The ICH4 automatically disables the port when the over-current active bit
is 1.
4 0 = This port does not have an over-current condition. This bit will automatically transition from a
1-to-0 when the over current condition is removed. (Default)
1 = This port currently has an over-current condition.
Port Enable/Disable Change — R/WC. For the root hub, this bit gets set to a 1 only when a port is
disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the
Universal Serial Bus (USB) Specification, Revision 2.0 for the definition of a port error). This bit is
3 _{not set due to the Disabled-to-Enabled transition, nor due to a disconnect.}
0 = No change in status. (Default). Software clears this bit by writing a 1 to it.
1 = Port enabled/disabled status has changed.
Port Enabled/Disabled — R/W. Ports can only be enabled by the host controller as a part of the
reset and enable. Software cannot enable a port by writing a 1 to this field. Ports can be disabled by
either a fault condition (disconnect event or other fault condition) or by host software. Note that the
2 ^{bit status does not change until the port state actually changes. There may be a delay in disabling or}
enabling a port due to other host controller and bus events.
0 = Disable. (Default)
1 = Enable.
Connect Status Change — R/WC. A 1 indicates a change has occurred in the port’s Current
Connect Status. The host controller sets this bit for all changes to the port device connect status,
even if system software has not cleared an existing connect status change. For example, the
1 ^{insertion status changes twice before system software has cleared the changed condition, hub}
hardware will be “setting” an already-set bit (i.e., the bit will remain set).
0 = No change. (Default). Software sets this bit to 0 by writing a 1 to it.
1 = Change in Current Connect Status.
Current Connect Status — RO. This value reflects the current state of the port, and may not
correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set.
0 _{0 = No device is present. (Default)}
1 = Device is present on port.
446
Intel^® 82801DB ICH4 Datasheet