82801DB Datasheet, PDF (468/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

AC ’97 Audio Controller Registers (D31:F5)
14.1.1
14.1.2
Core Well registers not reset by the D3_HOT to D0 transition:
• offset 2Ch–2Dh: Subsystem Vendor ID (SVID)
• offset 2Eh–2Fh: Subsystem ID (SID)
• offset 40h: Programmable Codec ID (PCID)
• offset 41h: Configuration (CFG)
Resume Well registers will NOT be reset by the D3_HOT to D0 transition:
• offset 54h–55h: Power Management Control and Status (PCS)
• Bus Mastering Register: Global Status Register, bits 17:16
• Bus Mastering Register: SDATA_IN MAP register, bits 7:3
VID—Vendor Identification Register (Audio—D31:F5)
Offset:
Default Value:
Lockable:
00–01h
8086h
No
Attribute:
Size:
Power Well:
RO
16 Bits
Core
Bit
Description
15:0 Vendor Identification Value — RO. This is a 16-bit value assigned to Intel.
DID—Device Identification Register (Audio—D31:F5)
Offset:
Default Value:
Lockable:
02–03h
24C5h
No
Attribute:
Size:
Power Well:
RO
16 Bits
Core
Bit
15:0 Device Identification Value — RO.
Description
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Intel^® 82801DB ICH4 Datasheet