82801DB Datasheet, PDF (62/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Intel^® ICH4 Power Planes and Pin States
Table 3-4. Power Plane and States for Output and I/O Signal (Sheet 4 of 4)
Signal Name
Power
Plane
During
PCIRST#⁴ /
RSMRST#^5,7
Immediately
after
PCIRST#⁴ /
RSMRST#⁵
S1
Unmuxed GPIO Signals
GPIO[18]
Main I/O
High
See Note 2 Defined
GPIO[19:20]
Main I/O
High
High
Defined
GPIO[21]
Main I/O
High
High
Defined
GPIO[22]
Main I/O
High-Z
High-Z
Defined
GPIO[23]
Main I/O
Low
Low
Defined
GPIO[24]
Resume I/O
High
High
Defined
GPIO[25]
Resume I/O
High
High
Defined
GPIO[27:28]
Resume I/O
High
High
Defined
GPIO[32:43]
Main I/O
High
High
Defined
S3
Off
Off
Off
Off
Off
Defined
Defined
Defined
Off
S4/S5
Off
Off
Off
Off
Off
Defined
Defined
Defined
Off
NOTES:
1. ICH4 sets these signals at reset for processor frequency strap.
2. GPIO[18] will toggle at a frequency of approximately 1 Hz when the ICH4 comes out of reset
3. CPUPWRGD is an open-drain output that represents a logical AND of the ICH4’s VRMPWRGD and
PWROK signals, and thus will be driven low by ICH4 when either VRMPWRGD or PWROK are inactive.
During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to
High-Z.
4. The states of main I/O signals are taken at the times During PCIRST# and Immediately after PCIRST#.
5. The states of resume I/O signals are taken at the times During RSMRST# and Immediately after RSMRST#.
6. SLP_5# is high in the S4 state and asserted low in the S5 state.
7. SUSCLK is running during PCIRST#, but is driven low during RSMRST#.
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Intel^® 82801DB ICH4 Datasheet