82801DB Datasheet, PDF (507/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

AC ’97 Modem Controller Registers (D31:F6)
15.2.8
GLOB_CNT—Global Control Register
I/O Address:
Default Value:
Lockable:
MBAR + 3Ch
00000000h
No
Attribute:
Size:
Power Well:
Reads across DWord boundaries are not supported.
R/W
32 bits
Core
Bit
Description
31:7 Reserved.
AC_SDIN2 Interrupt Enable (S2RE) — R/W.
6
0 = Disable.
1 = Enable an interrupt to occur when the codec on AC_SDIN[2] causes a resume event on the
AC-link.
AC_SDIN1 Resume Interrupt Enable (S1RE) — R/W.
5
0 = Disable.
1 = Enable an interrupt to occur when the codec on AC_SDIN[1] causes a resume event on the
AC-link.
AC_SDIN0 Resume Interrupt Enable (S0RE) — R/W.
4
0 = Disable.
1 = Enable an interrupt to occur when the codec on AC_SDIN[0] causes a resume event on the
AC-link.
ACLINK Shut Off (LSO) — R/W.
3 0 = Normal operation.
1 = Controller disables all outputs which will be pulled low by internal pull down resistors.
AC ’97 Warm Reset — R/W-Special.
0 = Normal operation.
1 = Writing a 1 to this bit causes a warm reset to occur on the AC-link. The warm reset will awaken
2
a suspended codec without clearing its internal registers. If software attempts to perform a
warm reset while bit_clk is running, the write will be ignored and the bit will not change. This bit
is self-clearing (it remains set until the reset completes and bit_clk is seen on the ACLink, after
which it clears itself).
AC ’97 Cold Reset# — R/W.
0 = Writing a 0 to this bit causes a cold reset to occur throughout the AC ‘97 circuitry. All data in
the controller and the codec will be lost. Software needs to clear this bit no sooner than the
minimum number of ms have elapsed.
1
1 = This bit defaults to 0 and hence after reset, the driver needs to set this bit to a 1. The value of
this bit is retained after suspends; hence, if this bit is set to a 1 prior to suspending, a cold reset
is not generated automatically upon resuming.
NOTE: This bit is in the Core well.
GPI Interrupt Enable (GIE) — R/W. This bit controls whether the change in status of any GPI
causes an interrupt.
0
0 = Bit 0 of the Global Status Register is set, but no interrupt is generated.
1 = The change on value of a GPI causes an interrupt and sets bit 0 of the Global Status Register.
Intel^® 82801DB ICH4 Datasheet
507