82801DB Datasheet, PDF (530/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Electrical Characteristics
Table 17-11. Ultra ATA Timing (Mode 0, Mode 1, Mode 2)
Sym
Parameter ⁽¹⁾
Mode 0 (ns) Mode 1 (ns)
Min Max Min Max
Mode 2 (ns)
Min Max
Measuring
Location
Figure
t80
Sustained Cycle Time
(T2cyctyp)
t81 Cycle Time (Tcyc)
240
112
t82 Two Cycle Time (T2cyc)
230
t83a Data Setup Time (Tds)
15
Recipient IC data setup time
t83b
(from data valid until
STROBE edge) (see Note 2)
14.7
(Tdsic)
t84a Data Hold Time (Tdh)
5
Recipient IC data hold time
t84b
(from STROBE edge until
data may become invalid)
4.8
(see Note 2) (Tdhic)
t85a
Data Valid Setup Time
(Tdvs)
70
Sender IC data valid setup
t85b
time (from data valid until
STROBE edge) (see Note 2)
72.9
(Tdvsic)
t86a Data Valid Hold Time (Tdvh) 6.2
Sender IC data valid hold
t86b
time (from STROBE edge
until data may become
9
invalid) (see Note 2) (Tdvhic)
t87 Limited Interlock Time (Tli)
0 150
t88
Interlock Time w/ Minimum
(Tmli)
20
t89 Envelope Time (Tenv)
20 70
t90 Ready to Pause Time (Trp) 160
t91
DMACK setup/hold Time
(Tack)
20
t92a
CRC Word Setup Time at
Host (Tcvs)
70
CRC word valid hold time at
sender (from DMACK#
t92b negation until CRC may
6.2
become invalid) (see Note 2)
(Tcvh)
160
73
153
10
9.7
5
4.8
48
50.9
6.2
9
0 150
20
20 70
125
20
48
6.2
120
54
115
7
Sender
Connector
End
Recipient
Connector
Sender
Connector
Recipient
Connector
6.8
ICH4 ball
5
Recipient
Connector
4.8
ICH4 ball
31
Sender
Connector
33.9
ICH4 ball
6.2
Sender
Connector
9
ICH4 ball
0 150 See Note 2
20
Host
Connector
20
70
Host
Connector
100
Recipient
Connector
20
Host
Connector
31
Host
Connector
6.2
Host
Connector
17-11
17-11
17-11
17-11
17-11
17-11
17-13
17-13
17-10
17-12
17-10,
17-13
530
Intel^® 82801DB ICH4 Datasheet