82801DB Datasheet, PDF (533/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Electrical Characteristics
Table 17-12. Ultra ATA Timing (Mode 3, Mode 4, Mode 5)
Sym
Parameter ⁽¹⁾
Mode 3 (ns)
Min Max
Mode 4 (ns)
Min Max
Mode 5 (ns)
Min Max
Measuring
Location
CRC Word Hold Time at
Sender
CRC word valid hold time at
t92b _{sender (from DMACK#}
6.2
negation until CRC may
become invalid)
(see Note 2) (Tcvh)
6.2
10.0
Host
Connector
STROBE output released-to-
t93 driving to the first transition
0
of critical timing (Tzfs)
0
35
Device
Connector
Data Output Released-to-
t94
Driving Until the First
Transition of Critical Timing
20.0
6.7
(Tdzfs)
25
Sender
Connector
t95
Unlimited Interlock Time
(Tui)
0
0
0
Host
Connector
Maximum time allowed for
t96a
output drivers to release
(from asserted or negated)
(Taz)
t96b
Drivers to assert or negate
(from released) (Tzad)
10
10
10 See Note 2
0
0
0
Device
Connector
Ready-to-final-STROBE time
t97
(no STROBE edges shall be
sent this long after negation
60
60
50
Sender
Connector
of DMARDY#) (Trfs)
t98a
Maximum time before
releasing IORDY (Tiordyz)
20
20
20
Device
Connector
Minimum time before driving
t98b IORDY
0
(see Note 2) (Tziordy)
0
0
Device
Connector
Time from STROBE edge to
negation of DMARQ or
t99 assertion of STOP (when
50
sender terminates a burst)
50
50
Sender
Connector
(Tss)
Figure
NOTES:
1. The specification symbols in parentheses correspond to the AT Attachment - 6 with Packet Interface (ATA/
ATAPI - 6) specification name.
2. See the AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) specification for further details on measuring
these timing parameters.
Intel^® 82801DB ICH4 Datasheet
533