82801DB Datasheet, PDF (263/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LAN Controller Registers (B1:D8:F0)
Bit
Description
Receive Not Ready (RNR) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
12 _{1 = Interrupt signaled because the Receive Unit left the Ready state. This may be caused by an RU}
Abort command, a no resources situation, or set suspend bit due to a filled Receive Frame
Descriptor.
Management Data Interrupt (MDI) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
11 _{1 = Set when a Management Data Interface read or write cycle has completed. The management}
data interrupt is enabled through the interrupt enable bit (bit 29 in the Management Data
Interface Control register in the CSR).
Software Interrupt (SWI) — R/WC.
10 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Set when software generates an interrupt.
Early Receive (ER) — R/WC.
9 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Indicates the occurrence of an Early Receive Interrupt.
Flow Control Pause (FCP) — R/WC.
8 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Indicates Flow Control Pause interrupt.
Command Unit Status (CUS) — RO.
00 = Idle
7:6 _{01 = Suspended}
10 = LPQ (Low Priority Queue) active
11 = HPQ (High Priority Queue) active
Receive Unit Status (RUS) —RO.
0000 = Idle
1000 = Reserved
0001 = Suspended
1001 = Suspended with no more RBDs
0010 = No Resources 1010 = No resources due to no more RBDs
5:2 _{0011 = Reserved}
1011 = Reserved
0100 = Ready
1100 = Ready with no RBDs present
0101 = Reserved
1101 = Reserved
0110 = Reserved
1110 = Reserved
0111 = Reserved
1111 = Reserved
1:0 Reserved
Intel^® 82801DB ICH4 Datasheet
263