82801DB Datasheet, PDF (353/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.8.3 Power Management I/O Registers
Table 9-10 shows the registers associated with ACPI and Legacy power management support.
These registers are enabled in the PCI Device 31: Function 0 space (PM_IO_EN), and can be
moved to any I/O location (128-byte aligned). The registers are defined to be compliant with the
ACPI 1.0 specification, and use the same bit names.
Note: All reserved bits and registers will always return 0 when read, and will have no effect when written.
Table 9-10. ACPI and Legacy I/O Register Map
PMBASE
+ Offset
Register Name
00–01h Power Management 1 Status
02–03h Power Management 1 Enable
04–07h Power Management 1 Control
08–0Bh Power Management 1 Timer
0Ch Reserved
10h–13h Processor Control
14h Level 2 Register
15h–16h Reserved
17–1Fh Reserved
20h Reserved
28–2Bh General Purpose Event 0 Status
2C–2Fh General Purpose Event 0 Enables
30–33h SMI# Control and Enable
34–37h SMI Status Register
38–39h Alternate GPI SMI Enable
3A–3Bh Alternate GPI SMI Status
3C–3Fh Reserved
40h Monitor SMI Status
42h Reserved
44h Device Trap Status
48h Trap Enable register
4Ch–4Dh Bus Address Tracker
4Eh Bus Cycle Tracker
50h Reserved
51h–5Fh Reserved
60h–7Fh Reserved for TCO Registers
ACPI Pointer
Default
Attributes
PM1a_EVT_BLK
PM1a_EVT_BLK+2
PM1a_CNT_BLK
PMTMR_BLK
0000h
0000h
00000000h
00000000h
R/WC
R/W
R/W, WO
RO
P_BLK
P_BLK+4
00000000h
00h
R/W, RO
RO
GPE0_BLK
GPE0_BLK+4
00000000h
00000000h
00000000h
00000000h
0000h
0000h
0000h
0000h
R/W, R/WC
R/W
R/W, WO,
R/W-Special
R/WC, RO
R/W
R/WC
RO
R/W, R/WC
0000h
R/W
0000h
R/W
Last Cycle
RO
Last Cycle
RO
Intel^® 82801DB ICH4 Datasheet
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