82801DB Datasheet, PDF (387/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

IDE Controller Registers (D31:F1)
10.1.9
MLT — Master Latency Timer Register (IDE—D31:F1)
Address Offset: 0Dh
Default Value: 00h
Attribute: RO
Size:
8 bits
Bit
Description
7:0
Master Latency Timer Count (MLTC) — RO. Hardwired to 00h. The IDE controller is implemented
internally, and is not arbitrated as a PCI device, so it does not need a Master Latency Timer.
10.1.10
.
PCMD_BAR—Primary Command Block Base Address
Register (IDE—D31:F1)
Address Offset: 10h–13h
Default Value:
00000001h
Attribute: R/W
Size:
32 bits
Bit
31:16
15:3
2:1
0
Description
Reserved
Base Address — R/W. Base address of the I/O space (8 consecutive I/O locations).
Reserved
Resource Type Indicator (RTE) — RO. his bit is set to one, indicating a request for I/O space.
NOTE: This 8-byte I/O space is used in native mode for the Primary controller’s Command Block.
10.1.11
.
PCNL_BAR—Primary Control Block Base Address Register
(IDE—D31:F1)
Address Offset: 14h–17h
Default Value:
00000001h
Attribute: R/W
Size:
32 bits
Bit
31:16
15:2
1
0
Description
Reserved
Base Address — R/W. Base address of the I/O space (4 consecutive I/O locations).
Reserved
Resource Type Indicator (RTE) — RO. This bit is set to one, indicating a request for I/O space.
NOTE: This 4-byte I/O space is used in native mode for the Primary controller’s Command Block.
Intel^® 82801DB ICH4 Datasheet
387