82801DB Datasheet, PDF (539/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Electrical Characteristics
17.5
6. If the transition to S5 is due to Power Button Override, SLP_S3#, SLP_S4# and SLP_S5# are asserted
together similar to timing t194 (PCIRST# active to SLP_S3# active).
7. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay
from RTCRST# and RSMRST# inactive to SUSCLK toggling may be as much as 2.5 seconds.
8. This value is programmable in multiples of 1024 PCI CLKs. Maximum is 8192 PCI CLKs (245.6 µs).
Timing Diagrams
Figure 17-1. Clock Timing
High Time
2.0V
0.8V
Fall Time
Period
Low Time
Rise Time
Figure 17-2. Valid Delay from Rising Clock Edge
Clock
Output
1.5V
Valid Delay
VT
Figure 17-3. Setup and Hold Times
Clock
1.5V
Input
Setup Time Hold Time
VT
VT
Intel^® 82801DB ICH4 Datasheet
539