82801DB Datasheet, PDF (196/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.17.1.3
5.17.1.4
Driver Initialization
See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal Serial Bus.
EHC Resets
In addition to the standard ICH4 hardware resets, portions of the EHC are reset by the HCRESET
bit and the transition from the D3hot device power management state to the D0 state. The effects of
each of these resets are listed in the following table.
Reset
HCRESET bit set
Software writes the
Device Power State
from D3hot (11b) to
D0 (00b)
Does Reset
Memory space
registers except
Structural Parameters
(which is written by
BIOS)
Does not Reset
Configuration
registers
Core well registers
(except BIOS-
programmed registers)
Suspend well
registers; BIOS-
programmed core
well registers
Comments
The HCRESET must only affect
registers that the EHCI driver controls.
PCI Configuration space and BIOS-
programmed parameters can not be
reset.
The D3-to-D0 transition must not cause
wake information (suspend well) to be
lost. It also must not clear BIOS-
programmed registers because BIOS
may not be invoked following the D3-to-
D0 transition.
If the detailed register descriptions give exceptions to these rules, those exceptions override these
rules. This summary is provided to help explain the reasons for the reset policies.
5.17.2
Data Structures in Main Memory
See Chapter 3 and Appendix B of the Enhanced Host Controller Interface Specification for
Universal Serial Bus for details.
5.17.3
USB 2.0 Enhanced Host Controller DMA
The ICH4 USB 2.0 EHC implements three sources of USB packets. They are, in order of priority
on USB during each microframe,
1. the USB 2.0 Debug Port (see Section USB 2.0 EHCI Based Debug Port),
2. the Periodic DMA engine, and
3. the Asynchronous DMA engine.
The ICH4 always performs any currently-pending debug port transaction at the beginning of a
microframe, followed by any pending periodic traffic for the current microframe. If there is time
left in the microframe, then the EHC performs any pending asynchronous traffic until the end of
the microframe (EOF1). Note that the debug port traffic is only presented on one port (Port #0),
while the other ports are idle during this time.
The following subsections describe the policies of the periodic and asynchronous DMA engines.
196
Intel^® 82801DB ICH4 Datasheet