82801DB Datasheet, PDF (284/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.20
8.1.21
8.1.22
8.1.23
PREF_MEM_MLT—Prefetchable Memory Limit Register
(HUB-PCI—D30:F0)
Offset Address: 26h–27h
Default Value: 00000000h
Attribute:
Size:
R/W
16 bit
Bit
Description
15:4
Prefetchable Memory Address Limit — RW. Defines the limit address of the prefetchable memory
address range for PCI. These 12 bits correspond to address bits 31:20.
3:0 Reserved. RO
IOBASE_HI—I/O Base Upper 16 Bits Register
(HUB-PCI—D30:F0)
Offset Address: 30–31h
Default Value: 0000h
Attribute:
Size:
RO
16 bits
Bit
Description
15:0 I/O Address Base Upper 16 Bits [31:16] — RO. Not supported; hardwired to 0.
IOLIM_HI—I/O Limit Upper 16 Bits Register
(HUB-PCI—D30:F0)
Offset Address: 32–33h
Default Value: 0000h
Attribute:
Size:
RO
16 bits
Bit
Description
15:0 I/O Address Limit Upper 16 Bits [31:16] — RO. Not supported; hardwired to 0.
INT_LINE—Interrupt Line Register (HUB-PCI—D30:F0)
Offset Address: 3Ch
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Interrupt Line (INT_LN) — RO. Hardwired to 00h. The bridge does not generate interrupts, and
interrupts from downstream devices are routed around the bridge.
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Intel^® 82801DB ICH4 Datasheet